- 16 8月, 2016 40 次提交
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由 Stefan Roese 提交于
This patch adds support for the DFI BayTrail BT700 QSeven SoM installed on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton NCT6102D Super IO chip providing the UART as console. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This patch includes the following changes: - Remove Designware I2C support from dts as its not used - Configure SMBus PADs in dts - Enable I2C commands and I2C support - Configure SMSC2513 USB hub via SMBus upon startup - Move environment location to match Minnowmax example - Enhancement of the default environment Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This patch adds support for the SMBus block read/write functionality. Other protocols like the SMBus quick command need to get added if this is needed. This patch also removed the SMBus related defines from the Ivybridge pch.h header. As they are integrated in this driver and should be used from here. This change is added in this patch to avoid compile breakage to keep the source git bisectable. Tested on a congatec BayTrail board to configure the SMSC2513 USB hub. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Yaroslav K 提交于
This fixes incorrect filenames in cbfsls output. Signed-off-by: NYaroslav K. <yar444@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> [clean up checkpatch errors and warnings] Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
These are not useful on x86 so do not print them. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
There is no sense in printing out DRAM banks of size 0 since this means they are empty. Skip them. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Without PS/2 keyboard and mouse in the ASL file, Windows does not see them. No problem for Linux as it probes keyboard and mouse via the legacy 8042 I/O port. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 George McCollister 提交于
Explicitly enable ILB_SERIRQ function 1 in cfio_regs_pad_ilb_serirq_PCONF0. Pad configuration for SERIRQ is not set to enable the SERIRQ function after a reset though strangely, it is on initial boot. Rebooting from Linux, reset command in u-boot and even pushing the reset button on the development board all lead to the SERIRQ function being disabled (address 0xfed0c560 with value of 0x2003cc80). Signed-off-by: NGeorge McCollister <george.mccollister@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This simple driver provides some functions to control some of the integrated devices. The watchdog is enabled per default. This driver adds a function to disable the watchdog. Also the internal legacy UART (io address 0x3f8/0x2f8) is enabled per default. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
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由 Stefan Roese 提交于
To support the BayTrail internal SIO HS UART, the internal UART clock needs to get configured. This patch adds support for this clock configuration which will be done, if the PCI device(s) are found. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE if it's undefined. This is needed for the xhci driver to compile. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This feature is not supported. Document this, and add some details on how it might be implemented. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
UEFI is commonly used on x86. Add a reference to U-Boot's support for this in the x86 README. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The README indicates that this is not supported, but this is no-longer true. Update the text to indicate this and describe the FIT changes required. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
The debug FSP image is bigger in size than the normal FSP image. This patch adds a small description on how to use this FSP debug version by changing CONFIG_FSP_ADDR. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
Add entry for the missing internal UART defconfig to the MAINTAINERS file. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Tom Rini 提交于
Now that nand_info[] is an array of pointers we need to ensure that it's been populated prior to use. We may for example have ENV in NAND set in configurations that run on boards with and without NAND (where default env is fine enough, such as omap3_beagle and beagleboard (NAND) vs beagle xM (no NAND)). Fixes: b616d9b0 ("nand: Embed mtd_info in struct nand_chip") Cc: Scott Wood <oss@buserror.net> Signed-off-by: NTom Rini <trini@konsulko.com> Acked-by: NScott Wood <oss@buserror.net>
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由 Andreas Fenkart 提交于
56086921 added support for unaligned environments access. U-boot itself does not support this: - env_nand.c fails when using an unaligned offset. It produces an error in nand_erase_opts{drivers/mtd/nand/nand_util.c} - in env_sf/env_flash the unused space at the end is preserved, but not in the beginning. block alignment is assumed - env_sata/env_mmc aligns offset/length to the block size of the underlying device. data is silently redirected to the beginning of a block There is seems no use case for unaligned environment. If there is some useful data at the beginning of the the block (e.g. end of u-boot) that would be very unsafe. If the redundant environments are hosted by the same erase block then that invalidates the idea of double buffering. It might be that unaligned access was allowed in the past, and that people with legacy u-boot are trapped. But at the time of 56086921 it wasn't supported and due to reasons above I guess it was never introduced. I prefer to remove that (unused) feature in favor of simplicity Signed-off-by: NAndreas Fenkart <andreas.fenkart@digitalstrom.com> Acked-by: NStefan Agner <stefan.agner@toradex.com>
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由 Chris Zankel 提交于
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: NChris Zankel <chris@zankel.net> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Max Filippov 提交于
DE212 is a general purpose xtensa processor without full MMU. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Max Filippov 提交于
DC233C is an xtensa processor with full MMUv3 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Chris Zankel 提交于
DC232B is an xtensa processor with full MMUv2 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: NChris Zankel <chris@zankel.net> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Chris Zankel 提交于
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: NChris Zankel <chris@zankel.net> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Chris Zankel 提交于
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: NChris Zankel <chris@zankel.net> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jon Medhurst \(Tixy\) 提交于
The firmware on TC2 needs to be configured appropriately before booting in nonsec mode will work as expected, so test for this and fall back to sec mode if required. Signed-off-by: NJon Medhurst <tixy@linaro.org> Reviewed-by: NRyan Harkin <ryan.harkin@linaro.org> Tested-by: NRyan Harkin <ryan.harkin@linaro.org>
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由 Wenyou Yang 提交于
Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Wenyou Yang 提交于
Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
Add device tree for SAMA5D2 Xplained board. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
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由 Wenyou Yang 提交于
Bring in required device tree file and bindings from Linux. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NAndreas Bießmann <andreas@biessmann.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAndreas Bießmann <andreas@biessmann.org>
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由 Wenyou Yang 提交于
Rework the driver to support driver model and device tree, and support to regard the pio4 pinctrl device as a child of atmel_pio4 device. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Wenyou Yang 提交于
In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andreas Bießmann 提交于
Fix compile warning for non OF_CONTROL builds: ---8<--- In file included from /Volumes/devel/u-boot/drivers/gpio/atmel_pio4.c:10:0: /Volumes/devel/u-boot/include/clk.h:107:12: warning: 'clk_get_by_name' defined but not used [-Wunused-function] --->8--- Signed-off-by: NAndreas Bießmann <andreas@biessmann.org> Acked-by: NStephen Warren <swarren@nvidia.com>
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由 Joe Hershberger 提交于
The cleanup of the legacy mii registration API that's no longer used now that the drivers have been converted to use the (more) modern API. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Joe Hershberger 提交于
If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Joe Hershberger 提交于
Some of the changes were a bit too complex. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Joe Hershberger 提交于
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Joe Hershberger 提交于
Many Ethernet drivers still use the legacy miiphy API to register their mdio interface for access to the mdio commands. This semantic patch will convert the drivers from the legacy adapter API to the more modern alloc/register API. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
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