xtensa: add support for the xtensa processor architecture [1/2]
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: NChris Zankel <chris@zankel.net> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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doc/README.xtensa
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