Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The recent global data changes (making the size autogenerated) broke the
board info handling on Blackfin ports as we were lying and lumping the
bd_t size in with the gd_t size.  So use the new dedicated bd_t size to
setup its own address in memory.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other
way around so that we can use CONFIG_ENV_OFFSET during build.  It also
avoids a little address duplication.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use
the one coming from the compiler.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Fixes a build error due to new partial linking logic.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NChong Huang <chuang@ucrobotics.com>
Signed-off-by: NHaitao Zhang <minipanda@linuxrobot.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Info about the hardware can be found here:
	http://www.dilnetpc.com/dnp0086.htmSigned-off-by: NAndreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Looks like the filesystem shuffling missed the SDP board.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This is a revert of 821ad16f as Wolfgang doesn't like the new code.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Unify this convention for all Blackfin boards.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We don't want/use this value for Blackfin boards, so punt it and have the
common code error out when people try to use it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Only the first run of boards had a ksz switch on it, so if building for a
newer silicon rev or SPI is disabled, don't bother checking for the ksz.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Conflicts:
	drivers/usb/host/ehci-pci.c
Signed-off-by: NWolfgang Denk <wd@denx.de>

Clean up the macro defintions used to enable DIU (video) support on the
MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS,
which is newer.  Add software cursor support to all three boards.

Also document the CONFIG_FSL_DIU_FB in the README.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Acked-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We implement our own mmc_get_env_addr since the environment variables are
written to just after the u-boot image on SDCard, so we must read the MBR
to get the start address and code length of the u-boot image, then
calculate the address of the env.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NZhao Chenhui <b35336@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On some boards the environment may not be located at a fixed address in
the MMC/SDHC card.  This allows those boards to implement their own
means to report what address the environment is located at.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NZhao Chenhui <b35336@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header.  This dramatically improves the
readability of the switch statments.

In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.

Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.

On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.

On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc.  Another 1.2kB of code comes in for
the function __umoddi3.

It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.

Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: NYork Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.
Signed-off-by: NLaurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NLi Yang <leoli@freescale.com>

Fix up the device tree property associated with the IEEE 1588 timer
source frequency.  Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support).  The eTSEC clock is ccb_clk/2.
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it.  Also we only have one Fman so no need for the code to deal with
a second.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage
device support using PCI EHCI module.
Signed-off-by: NZhao Chenhui <b35336@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NZhao Chenhui <b35336@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NZhao Chenhui <b35336@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

RevB boards never really made it outside of Freescale and have been
replaced with RevC & RevD which had various board bug fixes.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.

On board:
switch SW5[6] is to select width for eSDHC
        ON  - 4-bit [Enable eSPI]
        OFF - 8-bit [Disable eSPI]

switch SW4[8] is to select NOR Flash Bank for Booting
        OFF - Primary Bank
        ON  - Secondary Bank

Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
  size of image that could be loaded in SRAM mode and would require three
  stage boot loader (TPL).

Changes done:
 1. CONFIG_SYS_TEXT_BASE to 0x11000000
 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPoonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The NXID EEPROM format comes in two versions, v0 and v1.  The only
difference is in the number of MAC addresses that can be stored.  NXID v0
supports eight addresses, and NXID v1 supports 23.

Rather than allow a board to choose which version to support, NXID v0 is
now considered deprecated.  The EEPROM code is updated to support only
NXID v1, but it can still read EEPROMs formatted with v0.  In these cases,
the EEPROM data is loaded and the CRC is verified, but the data is stored
into a v1 data structure.  If the EEPROM data is written back, it is
written in v1 format.  This allows existing v0-formatted EEPROMs to
continue providing MAC addresses, but any changes to the data will force
an upgrade to the v1 format, while retaining all data.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>