Blackfin: BF50x: new processor port

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

arch/blackfin/cpu/gpio.c

@@ -45,7 +45,7 @@ static struct gpio_port_t * const gpio_array[] = {
 #if defined(BF533_FAMILY)
 	(struct gpio_port_t *) FIO_FLAG_D,
 #elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \
-	|| defined(BF538_FAMILY)
+	|| defined(BF538_FAMILY) || defined(CONFIG_BF50x)
 	(struct gpio_port_t *) PORTFIO,
 # if !defined(BF538_FAMILY)
 	(struct gpio_port_t *) PORTGIO,
@@ -71,7 +71,8 @@ static struct gpio_port_t * const gpio_array[] = {
 #endif
 };
 
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
+#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
+    defined(CONFIG_BF50x)
 static unsigned short * const port_fer[] = {
 	(unsigned short *) PORTF_FER,
 	(unsigned short *) PORTG_FER,
@@ -202,7 +203,8 @@ static void port_setup(unsigned gpio, unsigned short usage)
 	if (check_gpio(gpio))
 		return;
 
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
+#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
+    defined(CONFIG_BF50x)
 	if (usage == GPIO_USAGE)
 		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
 	else

arch/blackfin/cpu/initcode.c

@@ -341,13 +341,13 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 		return false;
 
 	/* If external memory is enabled, put it into self refresh first. */
-#ifdef EBIU_RSTCTL
+#if defined(EBIU_RSTCTL)
 	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 		serial_putc('b');
 		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 		return true;
 	}
-#else
+#elif defined(EBIU_SDGCTL)
 	if (bfin_read_EBIU_SDBCTL() & EBE) {
 		serial_putc('b');
 		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
@@ -373,12 +373,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	/* If we're entering self refresh, make sure it has happened. */
 	if (put_into_srfs)
-#ifdef EBIU_RSTCTL
+#if defined(EBIU_RSTCTL)
 		while (!(bfin_read_EBIU_RSTCTL() & SRACK))
-#else
+			continue;
+#elif defined(EBIU_SDGCTL)
 		while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
-#endif
 			continue;
+#else
+		;
+#endif
 
 	serial_putc('c');
 
@@ -536,7 +539,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 	/* Program the external memory controller before we come out of
 	 * self-refresh.  This only works with our SDRAM controller.
 	 */
-#ifndef EBIU_RSTCTL
+#ifdef EBIU_SDGCTL
 # ifdef CONFIG_EBIU_SDRRC_VAL
 	bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 # endif
@@ -552,9 +555,9 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	/* Now that we've reprogrammed, take things out of self refresh. */
 	if (put_into_srfs)
-#ifdef EBIU_RSTCTL
+#if defined(EBIU_RSTCTL)
 		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
-#else
+#elif defined(EBIU_SDGCTL)
 		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 #endif
 
@@ -646,10 +649,10 @@ program_async_controller(ADI_BOOT_DATA *bs)
 	serial_putc('b');
 
 	/* Not all parts have these additional MMRs. */
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MBSCTL_VAL
+#ifdef EBIU_MBSCTL
 	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-# endif
+#endif
+#ifdef EBIU_MODE
 # ifdef CONFIG_EBIU_MODE_VAL
 	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
 # endif

arch/blackfin/cpu/serial.h

@@ -31,13 +31,19 @@
 #define LOB(x) ((x) & 0xFF)
 #define HIB(x) (((x) >> 8) & 0xFF)
 
+#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
+# define BFIN_UART_HW_VER 2
+#else
+# define BFIN_UART_HW_VER 1
+#endif
+
 /*
  * All Blackfin system MMRs are padded to 32bits even if the register
  * itself is only 16bits.  So use a helper macro to streamline this.
  */
 #define __BFP(m) u16 m; u16 __pad_##m
 struct bfin_mmr_serial {
-#ifdef __ADSPBF54x__
+#if BFIN_UART_HW_VER == 2
 	__BFP(dll);
 	__BFP(dlh);
 	__BFP(gctl);
@@ -88,7 +94,7 @@ struct bfin_mmr_serial {
 #endif
 #define pUART ((volatile struct bfin_mmr_serial *)UART_DLL)
 
-#ifdef __ADSPBF54x__
+#if BFIN_UART_HW_VER == 2
 # define ACCESS_LATCH()
 # define ACCESS_PORT_IER()
 #else
@@ -107,7 +113,16 @@ static inline void serial_do_portmux(void)
 		return;
 	}
 
-#if defined(__ADSPBF51x__)
+#if defined(__ADSPBF50x__)
+# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
+	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \
+	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0: DO_MUX(G, 7, 7, 12, 13); break;	/* Port G; mux 7; PG12 and PG13 */
+	case 1: DO_MUX(F, 3, 3, 6, 7);   break;	/* Port F; mux 3; PF6 and PF7 */
+	}
+	SSYNC();
+#elif defined(__ADSPBF51x__)
 # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
 	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
 	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);

arch/blackfin/include/asm/blackfin_cdef.h

@@ -6,6 +6,12 @@
 #ifndef __MACH_CDEF_BLACKFIN__
 #define __MACH_CDEF_BLACKFIN__
 
+#ifdef __ADSPBF504__
+# include "mach-bf506/BF504_cdef.h"
+#endif
+#ifdef __ADSPBF506__
+# include "mach-bf506/BF506_cdef.h"
+#endif
 #ifdef __ADSPBF512__
 # include "mach-bf518/BF512_cdef.h"
 #endif

arch/blackfin/include/asm/blackfin_def.h

@@ -6,6 +6,16 @@
 #ifndef __MACH_DEF_BLACKFIN__
 #define __MACH_DEF_BLACKFIN__
 
+#ifdef __ADSPBF504__
+# include "mach-bf506/BF504_def.h"
+# include "mach-bf506/anomaly.h"
+# include "mach-bf506/def_local.h"
+#endif
+#ifdef __ADSPBF506__
+# include "mach-bf506/BF506_def.h"
+# include "mach-bf506/anomaly.h"
+# include "mach-bf506/def_local.h"
+#endif
 #ifdef __ADSPBF512__
 # include "mach-bf518/BF512_def.h"
 # include "mach-bf518/anomaly.h"

arch/blackfin/include/asm/mach-bf506/BF506_cdef.h

+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF506_proc__
+#define __BFIN_CDEF_ADSP_BF506_proc__
+
+#include "BF504_cdef.h"
+
+#endif /* __BFIN_CDEF_ADSP_BF506_proc__ */

arch/blackfin/include/asm/mach-bf506/BF506_def.h

+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF506_proc__
+#define __BFIN_DEF_ADSP_BF506_proc__
+
+#include "BF504_def.h"
+
+#endif /* __BFIN_DEF_ADSP_BF506_proc__ */

arch/blackfin/include/asm/mach-bf506/anomaly.h

+/*
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ */
+
+#if __SILICON_REVISION__ < 0
+# error will not work on BF506 silicon version
+#endif
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* UART IrDA Receiver Fails on Extended Bit Pulses */
+#define ANOMALY_05000447 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (1)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000257 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000283 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000315 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (0)
+#define ANOMALY_05000357 (0)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
+#define ANOMALY_05000371 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000440 (0)
+#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
+#define ANOMALY_05000485 (0)
+
+#endif

arch/blackfin/include/asm/mach-bf506/def_local.h

+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define CONFIG_BF50x 1	/* Linux glue */

arch/blackfin/include/asm/mach-bf506/gpio.h

+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 35
+
+#define GPIO_PF0	0
+#define GPIO_PF1	1
+#define GPIO_PF2	2
+#define GPIO_PF3	3
+#define GPIO_PF4	4
+#define GPIO_PF5	5
+#define GPIO_PF6	6
+#define GPIO_PF7	7
+#define GPIO_PF8	8
+#define GPIO_PF9	9
+#define GPIO_PF10	10
+#define GPIO_PF11	11
+#define GPIO_PF12	12
+#define GPIO_PF13	13
+#define GPIO_PF14	14
+#define GPIO_PF15	15
+#define GPIO_PG0	16
+#define GPIO_PG1	17
+#define GPIO_PG2	18
+#define GPIO_PG3	19
+#define GPIO_PG4	20
+#define GPIO_PG5	21
+#define GPIO_PG6	22
+#define GPIO_PG7	23
+#define GPIO_PG8	24
+#define GPIO_PG9	25
+#define GPIO_PG10	26
+#define GPIO_PG11	27
+#define GPIO_PG12	28
+#define GPIO_PG13	29
+#define GPIO_PG14	30
+#define GPIO_PG15	31
+#define GPIO_PH0	32
+#define GPIO_PH1	33
+#define GPIO_PH2	34
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */

arch/blackfin/include/asm/mach-bf506/portmux.h

+/*
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
+
+/* PPI Port Mux */
+#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
+#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
+#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
+#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+
+#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
+#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
+#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+
+#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+
+#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF13
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
+
+/* SPORT Port Mux */
+#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+
+#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+
+/* UART Port Mux */
+#ifdef CONFIG_BF506_UART0_PORTF
+#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#else
+#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#endif
+#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+
+#ifdef CONFIG_BF506_UART1_PORTG
+#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#else
+#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#endif
+#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+
+/* Timer */
+#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
+#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
+#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
+#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
+#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+
+/* CAN */
+#define P_CAN_TX	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_CAN_RX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+
+/* PWM */
+#define P_PWM0_AH	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PWM0_AL	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define P_PWM0_BH	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PWM0_BL	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PWM0_CH	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PWM0_CL	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PWM0_SYNC	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PWM0_TRIP	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+
+#define P_PWM1_AH	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_PWM1_AL	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_PWM1_BH	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
+#define P_PWM1_BL	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
+#define P_PWM1_CH	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
+#define P_PWM1_CL	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
+#define P_PWM1_SYNC	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+#define P_PWM1_TRIP	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
+
+/* RSI */
+#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+
+/* ACM */
+#define P_ACM_SE_DIFF	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_ACM_RANGE	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_ACM_A0	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_ACM_A1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_ACM_A2	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+
+#endif				/* _MACH_PORTMUX_H_ */

arch/blackfin/include/asm/mach-bf506/ports.h

+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x0003
+#define PORT_x_MUX_1_MASK	0x000C
+#define PORT_x_MUX_2_MASK	0x0030
+#define PORT_x_MUX_3_MASK	0x00C0
+#define PORT_x_MUX_4_MASK	0x0300
+#define PORT_x_MUX_5_MASK	0x0C00
+#define PORT_x_MUX_6_MASK	0x3000
+#define PORT_x_MUX_7_MASK	0xC000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+
+#endif

drivers/mmc/bfin_sdh.c

@@ -19,7 +19,7 @@
 #include <asm/mach-common/bits/sdh.h>
 #include <asm/mach-common/bits/dma.h>
 
-#if defined(__ADSPBF51x__)
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
 # define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CONTROL
 # define bfin_write_SDH_PWR_CTL		bfin_write_RSI_PWR_CONTROL
 # define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CONTROL

drivers/spi/bfin_spi.c

@@ -248,6 +248,8 @@ void spi_release_bus(struct spi_slave *slave)
 #elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
       defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
 # define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
+# elif defined(__ADSPBF50x__)
+# define SPI_DMA_BASE DMA6_NEXT_DESC_PTR
 #else
 # error "Please provide SPI DMA channel defines"
 #endif