Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Add support for fetching the clock frequency both using the legacy
method in case clock framework is disabled as well as via the clock
framework if it is enabled. This allows for migration to the clock
framework on platforms which supports it while not breaking legacy
platforms. That said, the legacy method must be removed eventually.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Enable DM ethernet framework on Arria10, so that the designware GMAC
can be probed from DT as it should be.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Remove code from the reset manager that is never called.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>

The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The I2Cx resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs
to work and add GMAC2 reset and OCP resets which were missing altogether.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Fixes: c859f2a7 ("arm: socfpga: Restructure the SPL file")

Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

In spl_gen5's board_init_f(), gd->malloc_base is manually assigned
at the end of the function to point to sdram.  This code is outdated
as by now, the heap is switched to sdram by the common function
spl_relocate_stack_gd() if the appropriate defines are set.

As it was, the value assigned manually was directly overwritten by
this common code, so remove the manual assignment.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
  because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
  dm_init (or one of its relatives) has not been called.

All this is fixed by calling spl_early_init before calling
preloader_console_init.

This fixes commit 73172753 ("ARM: socfpga: Convert to DM serial")
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Travis CI now supports giving jobs an explicit name. Do this for all jobs.
This allows more direct control over jobs names than the previous
automatic or implicit naming based on the environment variables or script
text.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
[trini: Update names for jobs added/changed since posting]
Signed-off-by: NTom Rini <trini@konsulko.com>

This update adds PPC64 ELF V1 ABI support to bootelf for both the
program header and section header options. Elf64 support was already
present for the program header option, but it was not handling the
PPC64 ELF V1 ABI case. For the PPC64 ELF V1 ABI, the e_entry field of
the elf header must be treated as function descriptor pointer instead
of a function address. The first doubleword of the function descriptor
is the function's entry address.
Signed-off-by: NRob Bracero <robbracero@gmail.com>
[trini: Fix whitespace issues]
Signed-off-by: NTom Rini <trini@konsulko.com>

Call the MSM DRAM detection and fixup function to support
dynamic detection of onboard memory.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Fixup the Linux FDT with the detection of onboard DRAM as
provided by SBL (Secondary boot loader) by reading
the shared-memory region.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Underlying API should already print some meaningful error message, so
this one is just brings more noise. E.g. we can see log like this:

    MMC: no card present
    ** Bad device mmc 0 **

Obviously, second error message is unwanted. Let's only print it in case
when DEBUG is defined to keep log short and clear.
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>

"Failed" error message from env_load() only clutters the log with
unnecessary details, as we already have all needed warnings by that
time. Example:

    Loading Environment from FAT... MMC: no card present
    ** Bad device mmc 0 **
    Failed (-5)

Let's only print it in case when DEBUG is defined to keep log clear.
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>

Fixes the following checkstyle warning:

WARNING: Missing a blank line after declarations
+               int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++);
+               max_struct_size = max(max_struct_size, tmp);
Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Fixes the following chechpatch -f error:

ERROR: "(foo*)" should be "(foo *)"
+               strncpy((char*)t->uuid, serial_str, sizeof(t->uuid));
Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Compressed images should have their compression property
set to "none" if U-Boot should leave them compressed.

This is especially the case for compressed ramdisks that
should be uncompressed by the kernel only.
Signed-off-by: NSimon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

For these boards, the GPMC timings are more determined by
processor speed/type than the NAND/PoP memory.  This code
is never invoked, so disable the config option, so it doesn't
take the time to compile it in.
Signed-off-by: NAdam Ford <aford173@gmail.com>

CONFIG_SYS_NAND_ADDR is defined and never referenced. This patch
removes the dead code.
Signed-off-by: NAdam Ford <aford173@gmail.com>

The Sphinx documentation system uses restructured text.
Make the README.iscsi file compatible.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Create separate html pages for linker lists, the serial subsystem,
and the EFI subsystem.

Add a table of content.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Describe the interface of environment variable callback functions.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>