- 23 10月, 2014 25 次提交
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由 Simon Glass 提交于
Buses sometimes want to pass data to their children when they are probed. For example, a SPI bus may want to tell the slave device about the chip select it is connected to. Add a new function to permit the parent data to be supplied to the child. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Simon Glass 提交于
Buses need to iterate through their children in some situations. Add a few functions to make this easy. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Simon Glass 提交于
Add a SPI device which can be used for testing SPI flash features in sandbox. Also add a cros_ec device since with driver model the Chrome OS EC emulation will not otherwise be available. Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We will need the console before relocation, so mark it that way. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The defines at the top of the GPIO driver use single-character names for parameters which are not very descriptive. Improve these to use descriptive parameter names. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The wrong header is being included, thus requiring the code to re-declare the generic GPIO interface in each GPIO header. Fix this. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for s5p_goni. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for smdkc100. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We don't include the pinctrl functions for U-Boot as they use up quite a bit of space and are not used. We could instead perhaps eliminate this material with fdtgrep, but so far this tool has not made it to upstream. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Bring in required device tree files for pinctrl from Linux v3.14. These are initially unchanged and have a number of pieces not needed by U-Boot. Note that exynos5420 is renamed to exynos54xx here since we want to support exynos5422 also. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We should be consistent about this. The kernel has moved to #include which breaks error reporting to some extent but does allow us to include binding files. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Robert Baldyga 提交于
Add proper initialization of GPIO pins used by software i2c. Signed-off-by: NRobert Baldyga <r.baldyga@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
The driver model supports two ways for passing device parameters; Device Tree and platform_data (board file). Each driver should generally support both of them because some popular IPs are used on various platforms. Assume the following scenario: - The driver Foo is used on SoC Bar and SoC Baz - The SoC Bar uses Device Tree control (CONFIG_OF_CONTROL=y) - The SoC Baz does not support Device Tree; uses a board file In this situation, the device driver Foo should work with/without the device tree control. The driver should have .of_match and .ofdata_to_platdata members for SoC Bar, while they are meaningless for SoC Baz; therefore those device-tree control code should go inside #ifdef CONFIG_OF_CONTROL. The driver code will be like this: #ifdef CONFIG_OF_CONTROL static const struct udevice_id foo_of_match = { { .compatible = "foo_driver" }, {}, } static int foo_ofdata_to_platdata(struct udevice *dev) { ... } #endif U_BOOT_DRIVER(foo_driver) = { ... .of_match = of_match_ptr(foo_of_match), .ofdata_to_platdata = of_match_ptr(foo_ofdata_to_platdata), ... } This idea has been borrowed from Linux. (In Linux, this macro is defined in include/linux/of.h) Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
The header files include/dm/platdata.h and include/dm/uclass.h use ll_entry_declare(); therefore they depend on include/linker_lists.h. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
The header file include/linker_lists.h uses __aligned(); therefore it depends on include/linux/compiler.h Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
if (strncmp(name, entry->name, len)) continue; /* Full match */ if (len == strlen(entry->name)) return entry; is equivalent to: if (!strcmp(name, entry->name)) return entry; The latter is simpler. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
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由 Masahiro Yamada 提交于
The function uclass_add() checks uc_drv->ops as follows: if (uc_drv->ops) { dm_warn("No ops for uclass id %d\n", id); return -EINVAL; } It seems odd because it warns "No ops" when uc_drv->ops has non-NULL pointer. (Looks opposite.) Anyway, most of UCLASS_DRIVER entries have no .ops member. This check makes no sense. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
The struct udevice stands for a device, not a driver. The driver_info.name is a driver's name, which is referenced to bind devices. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 21 10月, 2014 1 次提交
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- 17 10月, 2014 10 次提交
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由 Ruchika Gupta 提交于
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ruchika Gupta 提交于
U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for P1010 SPI Flash Secure boot target. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> [York Sun: Modified subject to P1010RDB] Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 16 10月, 2014 3 次提交
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由 Jeroen Hofstee 提交于
The ipu display insists on having a lower_margin smaller then 2. If this is not the case it will attempt to force it and adjust the pixclk accordingly. This multiplies pixclk in Hz with the width and height, since this is typically a * 10^7 * b * 10^2 * c * 10^2 this will overflow the uint_32 and make things even worse. Since this is a bootloader and the adjustment is neglectible, just force it to two and warn about it. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Jeroen Hofstee 提交于
- fix debug pixel clk display and add unit - fix some comments Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Simon Glass 提交于
Add a block to avoid a build error with the variable declaration. Enable the option on sandbox to prevent an error being introduced in future. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 14 10月, 2014 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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