dm: exynos: dts: Adjust device tree files for U-Boot

The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.
Signed-off-by: NSimon Glass <sjg@chromium.org>

arch/arm/dts/exynos4210-pinctrl-uboot.dtsi

+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos4210-pinctrl";
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpy0: gpy0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};

arch/arm/dts/exynos4210.dtsi

@@ -21,6 +21,7 @@
 
 #include "exynos4.dtsi"
 #include "exynos4210-pinctrl.dtsi"
+#include "exynos4210-pinctrl-uboot.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";

arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi

+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpf0: gpf0 {
+			reg = <0xc180>;
+		};
+		gpj0: gpj0 {
+			reg = <0x240>;
+		};
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpk0: gpk0 {
+			reg = <0x40>;
+		};
+		gpm0: gpm0 {
+			reg = <0x260>;
+		};
+		gpy0: gpy0 {
+			reg = <0x120>;
+		};
+		gpx0: gpx0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_2: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	pinctrl_3: pinctrl@106E0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};

arch/arm/dts/exynos4x12.dtsi

@@ -19,6 +19,7 @@
 
 #include "exynos4.dtsi"
 #include "exynos4x12-pinctrl.dtsi"
+#include "exynos4x12-pinctrl-uboot.dtsi"
 
 / {
 	aliases {

arch/arm/dts/exynos5250-pinctrl-uboot.dtsi

+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	pinctrl_0: pinctrl@11400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpc4: gpc4 {
+			reg = <0x2e0>;
+		};
+		gpx0: gpx0 {
+			reg = <0xc00>;
+		};
+	};
+
+	pinctrl_1: pinctrl@13400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	pinctrl_2: pinctrl@10d10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpv2: gpv2 {
+			reg = <0x060>;
+		};
+		gpv4: gpv4 {
+			reg = <0xc0>;
+		};
+	};
+
+	pinctrl_3: pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};

arch/arm/dts/exynos5250.dtsi

@@ -7,6 +7,7 @@
 
 #include "exynos5.dtsi"
 #include "exynos5250-pinctrl.dtsi"
+#include "exynos5250-pinctrl-uboot.dtsi"
 
 / {
 	aliases {

arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi

+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+	/*
+	 * Replicate the ordering of arch/arm/include/asm/arch-exynos/gpio.h
+	 * TODO(sjg@chromium.org): This ordering ceases to matter once GPIO
+	 * numbers are not needed in U-Boot for exynos.
+	 */
+	pinctrl@14010000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@13400000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpy7 {
+		};
+
+		gpx0 {
+			reg = <0xc00>;
+		};
+	};
+	pinctrl@13410000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@14000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+	pinctrl@03860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+};

arch/arm/dts/exynos54xx-pinctrl.dtsi

@@ -12,6 +12,8 @@
  * published by the Free Software Foundation.
 */
 
+#include "exynos54xx-pinctrl-uboot.dtsi"
+
 / {
 	pinctrl@13400000 {
 		gpy7: gpy7 {

arch/arm/dts/exynos54xx.dtsi

@@ -6,6 +6,7 @@
  */
 
 #include "exynos5.dtsi"
+#include "exynos54xx-pinctrl.dtsi"
 
 / {
 	config {