- 06 12月, 2014 35 次提交
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由 Shengzhou Liu 提交于
T1024QDS is a high-performance computing evaluation, development and test platform for T1024 QorIQ Power Architecture processor. T1024QDS board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Three 1G/2.5Gbps SGMII ports - Four 1Gbps QSGMII ports - one 10Gbps XFI or 10Base-KR interface - SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora - PCIe: Three PCI Express controllers with five PCIe slots. - IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - Video: DIU supports video up to 1280x1024x32 bpp. - Chrontel CH7201 for HDMI connection. - TI DS90C387R for direct LCD connection. - Raw (not encoded) video connector for testing or other encoders. - QUICC Engine block - 32-bit RISC controller for flexible support of the communications peripherals - Serial DMA channel for receive and transmit on all serial channels - Two universal communication controllers, supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - eSPI: Three SPI flash devices. - SATA: one SATA 2.O. - USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC. - I2C: Four I2C controllers. - UART: Two UART on board. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Priyanka Jain 提交于
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0, and also update core frequency to 1.8GHz for v1.1. We reserve the support for T2080 v1.0 and enable v1.1 by default. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Suresh Gupta 提交于
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com> Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Suresh Gupta 提交于
SerDes2 lanes EFGH either go to SFP or AMC riser card slot2. By default AMC will be configured even if no hwconfig is specified. To enable XFI via SFP use the below hwconfig: fsl_b4860_serdes2:sfp_amc=sfp Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@ffeescale.com> Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
Since xfi has no phy, we delete the property "phy-handle" and use a "fixed-link" property for a xfi port. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
We need following changes to make xfi work on B4: 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 10G interface check for xfi; 3. set phy address for xfi so the 10G ports can be registered by mdio; Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
Add the support of newly added LC VCO SerDes protocols for configuration of IDT and VSC crossbar Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
- Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
Addded Alternate options with LC VCO for following protocols: 0x02 --> 0x01 0x08 --> 0x07 0x18 --> 0x17 0x1E --> 0x1D 0x49 --> 0x48 0x6F --> 0x6E 0x9A --> 0x99 0x9E --> 0x9D Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation for them only. Remove static LAW creation for MAPLE. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NSandeep Singh <Sandeep@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 vijay rai 提交于
Convert T1040QDS and T1040RDB to use generic board code. Signed-off-by: NVijay Rai <vijay.rai@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
Add configs: o CONFIG_SYS_GENERIC_BOARD o CONFIG_DISPLAY_BOARDINFO in C29XPCIE config header file to use U-boot generic board code. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
Add configs: o CONFIG_SYS_GENERIC_BOARD o CONFIG_DISPLAY_BOARDINFO in P1023RDB config header file to use U-boot generic board code. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tang Yuantian 提交于
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Heiko Schocher 提交于
cppcheck reports: [board/muas3001/muas3001.c:270]: (error) Uninitialized variable: psize remove the CONFIG_SYS_RAMBOOT define to prevent this error report. Signed-off-by: NHeiko Schocher <hs@denx.de> Reported-by: NWolfgang Denk <wd@denx.de> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Holger Brunck 提交于
This define is never set in our setup, so we can remove it safely. The former code causes cppcheck to complain about: [board/keymile/km82xx/km82xx.c:311]: (error) Uninitialized variable: psize Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Wolfgang Denk <wd@denx.de> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ying Zhang 提交于
Use generic board architecture for p1010rdb, tested with NOR boot on p1010rdb-pb. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
The define CONFIG_FSL_SATA_V2 is missing, so SATA is not available in U-boot. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ying Zhang 提交于
Use generic board architecture for p1025-twr, tested with NOR boot and NAND boot on p1025-twr. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ying Zhang 提交于
The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function has_errata_a007186 to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the sil has errata a007186, then run the errata code, if not, doesn't run the code. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Workaround of Errata A-008044 was implemented without errata number and it is enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0. So put errata number and make it conditional. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
When device is configured to load RCW from NAND flash IFC_A[16:31] are driven low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using IFC_A[16:31] lines are not accessible. Workaround is already in-place. Put the errata number to adhere errata handling framework. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Enable interactive debugging by default. Remove DDR controller interleaving because this SoC only has one controller. Use auto chip-select interleaving to detect number of ranks. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Poonam Aggrwal <poonam.aggrwal@freescale.com>
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由 York Sun 提交于
T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio, the same way as T4240 rev 2.0. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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由 York Sun 提交于
Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of 1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in case such DIMM comes available. Also update single-rank 1866 timing. Enable interactive debugging as well. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Shengzhou Liu 提交于
Add serdes2 protocol 0x2e. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Joakim Tjernlund 提交于
fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE. This excludes testing for SGMII further down. Remove the unconditional "else return PHY_INTERFACE_MODE_NONE" so SGMII can be tested too. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
To support interactive DDR debugger, cli_simple.o, cli.o, cli_readline.o, command.o, s_record.o, xyzModem.o and cmd_disk.o are all needed for drivers/ddr/fsl/interactive.c. In current common/Makefile, the above .o files are only produced when CONFIG_SPL_BUILD is disabled. For LS102xA, interactive DDR debugger is needed in SD/NAND boot too, and I enabled CONFIG_FSL_DDR_INTERACTIVE. But according to the current common/Makfile, all the above .o files are not produced in SPL part because CONFIG_SPL_BUILD is enabled in SPL part, the following error will be shown, drivers/ddr/fsl/built-in.o: In function `fsl_ddr_interactive': /home/wangh/layerscape/u-boot/drivers/ddr/fsl/interactive.c:1871: undefined reference to `cli_readline_into_buffer' /home/wangh/layerscape/u-boot/drivers/ddr/fsl/interactive.c:1873: undefined reference to `cli_simple_parse_line' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 So this patch fixed this issue and the above .o files will be produced no matter CONFIG_SPL_BUILD is enabled or disabled. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 27 11月, 2014 5 次提交
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由 Daniel Schwierzeck 提交于
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
The initramfs is currently only relocated if the user calls the bootm ramdisk subcommand. If bootm should be used without subcommands, the arch-specific bootm code needs to implement the relocation. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
After all MIPS boards are switched to generic-board, the MIPS specific board.c can be removed. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NStefan Roese <sr@denx.de>
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