- 10 1月, 2015 3 次提交
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由 Masahiro Yamada 提交于
Currently, "nand scrub" runs chip->scan_bbt at the end of nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set. It violates the intention of NAND_SKIP_BBTSCAN. Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set. Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt() right after scrub. We can be lazier here because the BBT is scanned at the next call of nand_block_checkbad(). Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
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由 Masahiro Yamada 提交于
Commit 35c204d8 (nand: reinstate lazy bad block scanning) broke NAND_BBT_USE_FLASH feature. Its git-log claimed that it reinstated the change as by commit fb49454b ("nand: reinstate lazy bad block scanning"), but it moved "chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);". It causes recursion if scan_bbt does not find a flash based BBT and tries to write one, and the attempt to erase the BBT area causes a bad block check. Reinstate commit ff49ea89 (NAND: Mark the BBT as scanned prior to calling scan_bbt.). Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rostislav Lisovy <lisovy@merica.cz> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com>
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由 Masahiro Yamada 提交于
Since commit ff94bc40 (mtd, ubi, ubifs: resync with Linux-3.14), the "nand scrub" command has not been working. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
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- 09 1月, 2015 13 次提交
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由 Stefan Agner 提交于
Boot from SD-card (and probably also from NAND) was broken since commit d6d07a9b ("arm: vf610: add NAND support for vf610twr"). It looks like the increased size of U-Boot lead to a situation where the boot ROM overwrote its own stack/heap while loading U-Boot from the SD-card to the SRAM. However, U-Boot worked fine when loaded through USB serial loader directly into SRAM. It looks like loading from SD-card uses other stack/heap location then the serial loader (or maybe no stack or heap at all). This fix moves U-Boot to gfxRAM, which is 512kB in size and is not used by the boot ROM nor the SD-card loader of it. Signed-off-by: NStefan Agner <stefan@agner.ch> Acked-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
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由 Stefan Agner 提交于
Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NStefan Agner <stefan@agner.ch>
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由 Fabio Estevam 提交于
Since commit 3ff46cc4 ("arm: relocate the exception vectors") mx25pdk hangs like this: CPU: Freescale i.MX25 rev1.2 at 399 MHz Reset cause: WDOG Board: MX25PDK I2C: ready DRAM: 64 MiB (hangs) Add a specific relocate_vectors macro that skips the vector relocation, as the i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows mx25 to boot again. Acked-By: NBill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Peng Fan 提交于
Add CONFIG_SYS_FSL_QSPI_AHB in header file to enable AHB in driver. In order to count the time, add CONFIG_CMD_TIME. Using AHB read can improve the the read speed about 30%. AHB read: => time sf read 0x8f800000 0 100000 SF: 1048576 bytes @ 0x0 Read: OK time: 0.174 seconds => time sf read 0x8f800000 1000000 100000 SF: 1048576 bytes @ 0x1000000 Read: OK time: 0.174 seconds IP read: => time sf read 0x8f800000 0 100000 SF: 1048576 bytes @ 0x0 Read: OK time: 0.227 seconds => time sf read 0x8f800000 1000000 100000 SF: 1048576 bytes @ 0x1000000 Read: OK time: 0.227 seconds Note: Quad read is not supported in driver, now. In my side, using AHB and Quad read can achieve about 16MB/s. Anyway, I have plan to reimplement the driver using DTB and DM, then make the code cleaner and more feature can be added. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Peng Fan 提交于
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using IP register and AHB bus. The original driver only supports reading data from IP interface. The IC team suggests to use AHB read which is faster then IP read. Using AHB read, we can directly memcpy, a "missed" access to the buffer will cause the controller to clear the buffer and use the SEQID stored in bfgencr register to initiate a read from flash device. Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little endian but not 32bit Little endia. Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it. Actually if Vybrid is migrated to use AHB read, this option can be removed and IP read function can be discared. The reason to introduce this option is that only i.MX SOC is tested in my side, no Vybrid platform for me. In spi_setup_slave, the original piece code to set AHB is deleted, since Vybrid platform does not use this to intiate AHB read. Instead, add qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Jeremiah Mahler 提交于
Fix several spelling errors and replace the invalid word "architectured" with "designed". Signed-off-by: NJeremiah Mahler <jmmahler@gmail.com>
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由 Fabio Estevam 提交于
Currently there is an unneeded empty line after printing the reset cause: U-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19) CPU: Freescale i.MX25 rev1.2 at 399 MHz Reset cause: POR Board: MX25PDK I2C: ready DRAM: 64 MiB MMC: FSL_SDHC: 0 Remove the extra "\n" when printing the reset cause. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Peng Fan 提交于
We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3, there are 4 i2c interface, but not 3. So the size of i2c_data array should be calculated using "ARRAY_SIZE(i2c_bases)". To avoid compile error, move i2c_bases before sram_data structure which contains i2c_data array. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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由 Luka Perkov 提交于
Signed-off-by: NLuka Perkov <luka.perkov@sartura.hr> CC: Prafulla Wadaskar <prafulla@marvell.com> CC: Wolfgang Denk <wd@denx.de> Acked-by: NStefan Roese <sr@denx.de>
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由 Luka Perkov 提交于
Signed-off-by: NLuka Perkov <luka.perkov@sartura.hr>
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由 Maxime Ripard 提交于
According to the UEFI Spec (Table 16, section 5.2.3 of the version 2.4 Errata B), the protective MBR partition record size must be set to the size of the disk minus one, in LBAs. However, the current code was setting the size as the total number of LBAs on the disk, resulting in an off-by-one error. This confused the AM335x ROM code, and will probably confuse other tools as well. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Bill Pringlemeir 提交于
Commit 73c25753 fixed the common issue that binutil packages (tool/organization that packaged or built the bin-utils) are included in brackets and this may falsely be recognized as a version. However, some tools do not provide a 'package' and previously we add the 'Gnu assembler..' to the version. Strip out the '(package version text)' and then look for a ##.## string. Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com> Tested-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: NHans de Goede <hdegoede@redhat.com>
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- 08 1月, 2015 5 次提交
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由 Masahiro Yamada 提交于
The low-level debugging functions are useful to debug the early boot stage where the full UART driver is not available. UniPhier SoCs need to initialize the UART port 0 to use this feature. The initialization routine is called at the very entry of the lowlevel_init(). Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs, the output of the system bus is disabled by default. It must be enabled by software to have access to the system bus. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
The max size of available memories on slot0 and slot1 is 32MB because - EA[25] signal is not output on the save-pin mode which is used PH1-LD4 or later SoCs. - EA[25] signal is not connected by the limitation (or bug?) of the PLD logic of DCC support card. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Axel Lin 提交于
No functional change, just simplify the code a bit. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Masahiro Yamada 提交于
Make it a sub-menu of "General setup" like Linux Kernel. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
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- 07 1月, 2015 4 次提交
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由 Axel Lin 提交于
fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found. 0 is supposed to be a valid offset returns from fdt_first_subnode(). Signed-off-by: NAxel Lin <axel.lin@ingics.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Peng Fan 提交于
mx6sxsabresd revb board uses 32MB qspi flash, reva board uses 16MB qspi flash. Currently, the default supported platform is revb board. If want to configure for reva board, just define CONFIG_MX6SX_SABRESD_REVA in mx6sxsabresd.h to support reva qspi flashes whose size is 16MB. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Peng Fan 提交于
To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Marek Vasut 提交于
This optional DT property is called 'num-cs', so repair the misnomers. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Acked-by: NPavel Machek <pavel@denx.de> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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- 06 1月, 2015 15 次提交
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由 Marek Vasut 提交于
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: NStefan Roese <sr@denx.de> Acked-by: NPavel Machek <pavel@denx.de> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Hans de Goede 提交于
This fixes us never programming ALDO2, and programming the ALDO2 voltage into ALDo1. Reported-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Axel Lin 提交于
Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code: 1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1. 2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary to test fifo == 257. In the case fifo is 257, it means the latest valid setting is fifo = 256. So after the for loop iteration, we should check fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails. This patch fixes above issues. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Guillaume GARDET 提交于
As reported by Robert Nelson, commit 4c5bbc23 may break MMC RAW boot mode. This patch fixes the check path to fix MMC Raw boot mode. Tested raw boot mode and FS boot mode on a pandaboard (rev. A3). Reported-by: NRobert Nelson <robertcnelson@gmail.com> Signed-off-by: NGuillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@ti.com> Cc: Robert Nelson <robertcnelson@gmail.com> Tested-by: NRobert Nelson <robertcnelson@gmail.com>
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由 Gerald Kerma 提交于
Remove unnessecary delay from mvebu_mmc_initialize Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Gerald Kerma 提交于
Clean mvebu_mmc_send_cmd Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Gerald Kerma 提交于
Remove delays in mvebu_mmc_set_bus and mvebu_mmc_set_clk Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Gerald Kerma 提交于
Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Gerald Kerma 提交于
Get about 40x faster access on SHEEVAPLUG MMC Fix some SD type compatibility Changes in v3: - fix the HW_STATE (from linux mvsdio) - review delays and timeouts Changes in v2: - increase number of loops - remove initial delay Changes in v1: - review all loops, delays and timeouts Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Gerald Kerma 提交于
Signed-off-by: NGérald Kerma <drEagle@doukki.net> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Tom Rini 提交于
We need <scsi.h> for scsi_scan(). Signed-off-by: NTom Rini <trini@ti.com>
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由 Sjoerd Simons 提交于
The ChromeOS EC keyboard is used by various different chromebooks. Peach pi being the third board in the u-boot tree to use it (snow and peach pit the other two). Rather then embedding the same big DT node in the peach-pi DT again, copy the dtsi snippit & bindings documentation from linux and include it in all 3 boards. This slightly changes the dt bindings in u-boot: * google,key-rows becomes keypad,num-rows * google,key-colums becomes keypad,num-colums * google,repeat-delay-ms and google,repeat-rate-ms are no longer used and replaced by hardcoded values (similar to tegra kbc) Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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