- 26 1月, 2016 1 次提交
-
-
由 Shengzhou Liu 提交于
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
-
- 19 1月, 2016 1 次提交
-
-
由 Tom Rini 提交于
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 14 12月, 2015 1 次提交
-
-
由 York Sun 提交于
DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 31 10月, 2015 1 次提交
-
-
由 Joakim Tjernlund 提交于
SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: NJoakim Tjernlund <joakim.tjernlund@transmode.se> Reviewed-by: NYork Sun <yorksun@freescale.com>
-
- 23 4月, 2015 2 次提交
-
-
由 York Sun 提交于
The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
-
由 York Sun 提交于
This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 12 12月, 2014 1 次提交
-
-
由 Tang Yuantian 提交于
With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
-
- 25 9月, 2014 2 次提交
-
-
由 York Sun 提交于
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
由 York Sun 提交于
U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 09 9月, 2014 1 次提交
-
-
由 York Sun 提交于
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 23 4月, 2014 2 次提交
-
-
由 Tang Yuantian 提交于
When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
-
由 York Sun 提交于
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 22 2月, 2014 1 次提交
-
-
由 York Sun 提交于
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 26 11月, 2013 1 次提交
-
-
由 York Sun 提交于
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 17 10月, 2013 1 次提交
-
-
由 Priyanka Jain 提交于
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
-
- 10 8月, 2013 2 次提交
-
-
由 York Sun 提交于
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
由 York Sun 提交于
On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 23 10月, 2012 3 次提交
-
-
由 York Sun 提交于
When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
由 York Sun 提交于
Fix handling quad-rank DIMMs in a system with two DIMM slots and first slot supports both dual-rank DIMM and quad-rank DIMM. For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config registers need to be enabled to maintain proper ODT operation. The inactive CS should have bnds registers cleared. Fix the turnaround timing for systems with all chip-selects enabled. This wasn't an issue before because DDR was running lower than 1600MT/s with this interleaving mode. Fix DDR address calculation. It wasn't an issue until we have multiple controllers with each more than 4GB and interleaving is disabled. It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off) when debugging DDR and first DDR controller is disabled. With the fix, the first enabled controller information will be displayed. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
由 York Sun 提交于
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be set for speed lower than 1250MT/s. CDR1 and CDR2 are control driver registers. ODT termination valueis for IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is 000 -> Termsel off 001 -> 120 Ohm 010 -> 180 Ohm 011 -> 75 Ohm 100 -> 110 Ohm 101 -> 60 Ohm 110 -> 70 Ohm 111 -> 47 Ohm Add two write leveling registers. Each QDS now has its own write leveling start value. In case of zero value, the value of QDS0 will be used. These values are board-specific and are set in board files. Extend DDR register timing_cfg_1 to have 4 bits for each field. DDR control driver registers and write leveling registers are added to interactive debugging for easy access. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
- 24 8月, 2012 1 次提交
-
-
由 York Sun 提交于
Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
- 23 8月, 2012 1 次提交
-
-
由 Matthew McClintock 提交于
Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
- 30 9月, 2011 2 次提交
-
-
由 York Sun 提交于
DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 12 7月, 2011 2 次提交
-
-
由 York Sun 提交于
Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
由 York Sun 提交于
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 05 4月, 2011 1 次提交
-
-
由 Zhao Chenhui 提交于
Signed-off-by: NZhao Chenhui <b35336@freescale.com> Acked-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 04 4月, 2011 2 次提交
-
-
由 Poonam Aggrwal 提交于
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 03 2月, 2011 1 次提交
-
-
由 York Sun 提交于
Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 20 1月, 2011 4 次提交
-
-
由 York Sun 提交于
Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 14 1月, 2011 2 次提交
-
-
由 Kumar Gala 提交于
Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Becky Bruce 提交于
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Tested-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 20 10月, 2010 1 次提交
-
-
由 York Sun 提交于
800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters, hwconfig=fsl_ddr:sdram=fixed To use SPD parameters, hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1 Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 27 7月, 2010 2 次提交
-
-
由 york 提交于
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
由 york 提交于
Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by: NYork Sun <yorksun@freescale.com>
-
- 27 4月, 2010 1 次提交
-
-
由 Dave Liu 提交于
add the macro definition for Rtt_Nom termination value for DDR3 Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-