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  1. 05 3月, 2014 2 次提交
    • P
      mtd: nand: omap: remove unused #defines from common omap_gpmc.h · a7e36fc9
      由 pekon gupta 提交于 
      OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI
params or nand_id[] table. And based on that it defines ECC layout.
This patch
1) removes following board configs used for defining NAND ECC layout
	- GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND)
	- GPMC_NAND_ECC_LP_x8_LAYOUT  (for large page x8 NAND)
	- GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND)
	- GPMC_NAND_ECC_SP_x8_LAYOUT  (for small page x8 NAND)

2) removes unused #defines in common omap_gpmc.h depending on above configs

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: NPekon Gupta <pekon@ti.com>
      a7e36fc9
    • P
      mtd: nand: omap: remove redundant platform specific header: arch-xx/omap_gpmc.h · 50899183
      由 pekon gupta 提交于 
      Currently there are two sets of omap_gpmc.h header files
(a) arch/arm/include/asm/omap_gpmc.h
 common header file for all platforms, containing defines and declarations used
 by GPMC NAND driver.

(b) arch/arm/include/asm/arch-xx/omap_gpmc.h
 SoC platform specific header file containing defines like ECC layout.

This patch removes platform specific arch-xx/omap_gpmc.c because:
 - GPMC hardware engine is common for all SoC platforms hence only (a) is enough
 - ECC layout is now defined in omap_nand.c driver itself based on ecc-scheme
   selected. Hence all ECC layout declarations in (b) are redundant.

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
Signed-off-by: NPekon Gupta <pekon@ti.com>
      50899183
  3. 04 3月, 2014 4 次提交
    • P
      board/ti/am335x/README: update for NAND boot · 32f4d729
      由 pekon gupta 提交于 
      NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this README
Signed-off-by: NPekon Gupta <pekon@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>
Acked-by: NTom Rini <trini@ti.com>
      32f4d729
    • P
      mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes · 6e562b11
      由 pekon gupta 提交于 
      chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
	for ECC_BCH8 scheme using GPMC and ELM

This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
  known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
  omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]
Signed-off-by: NPekon Gupta <pekon@ti.com>
      6e562b11
    • P
      mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes · 71a7f956
      由 pekon gupta 提交于 
      chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.

All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.

This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
  omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
				==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.
Signed-off-by: NPekon Gupta <pekon@ti.com>
      71a7f956
    • P
      mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes · f5f1f614
      由 pekon gupta 提交于 
      chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)

Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()

(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()
Signed-off-by: NPekon Gupta <pekon@ti.com>
      f5f1f614
  5. 27 2月, 2014 6 次提交
  7. 26 2月, 2014 21 次提交
  9. 25 2月, 2014 7 次提交