This patch enables DM_USB on the Marvell AXP / A38x eval boards.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds driver model (DM) support to the Marvell EHCI driver.
This will be used by the MVEBU SoC's, currently Armada XP and 38x.

Tested on Marvell Armada XP and 38x eval boards.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds driver model support for some Marvell MVEBU SoC's. Including
Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now
selected automatically for MVEBU platforms.

With this DM support now available for MVEBU, hardcoding the base addresses
and other information is not necessary any more. Probing should be done
by using the values provided via the device tree now instead. For this
the driver also need to be converted to DM. Patches for some of the drivers
will follow.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>

These will be needed by the upcoming DM (driver model) support for
the Armada XP / 38x SoC's. This will provide DT based probing.

The dts files are copied 1:1 from the Linux kernel release v4.2.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the MVEBU SPL with the correct SPL design as well as reduces
the stack utilisation slightly.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>

The MVEBU BootROM does not allow non word aligned payloads.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more complex "ranges"
properties are used in many nodes (multiple tuples etc). This patch
enables the optional use of the common fdt_translate_address() function
which handles this translation correctly.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables the use of the kwboot tool, to boot mainline U-Boot
on the Marvell Armada XP/38x SoC's. This is done by returning to the
SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
to not reconfigure the internal register space and MBARs. Otherwise
the BootROM will not be able to continue after SPL jumps back to it.

To use this feature, please don't forget to change the BOOT_FROM line
in your board specfic kwbimage.cfg file this way:

    BOOT_FROM uart

Tested on these Marvell eval boards:
DB-MV784MP-GP - Armada XP
DB-88F6820-GP - Armada 38x
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Introduce a mach-mvebu/Kconfig for all Armada based SoC's.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NTom Rini <trini@konsulko.com>

This code is no-longer used. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure.  A bisect led to commit 6eed3786
("net: Move the CMD_NET config to defconfigs").  This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:

 u-boot$git describe 6eed3786
 v2015.07-rc1-412-g6eed3786
              ^^^

 u-boot$ls -l ../41*/u-boot.bin
 -rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
 -rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
 u-boot$bc
 bc 1.06.95
 Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
 This is free software with ABSOLUTELY NO WARRANTY.
 For details type `warranty'.
 256*1024
 262144

i.e. we finally broke through the 256k monitor size.  Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.

We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

...so that I don't have to go work them out from scratch again
by peering at the manual.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k.  But the device sector
size is 1/2 that, as can be seen from "fli" output:

Bank # 1: CFI conformant flash (16 x 16)  Size: 16 MB in 131 Sectors
  Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888
  Erase timeout: 4096 ms, write timeout: 1 ms
  Buffer write timeout: 2 ms, buffer size: 64 bytes

  Sector Start Addresses:
  FF000000 E RO   FF020000 E RO   FF040000 E RO   FF060000 E RO   FF080000 E RO
  FF0A0000 E RO   FF0C0000 E RO   FF0E0000 E RO   FF100000 E RO   FF120000 E RO
  [...]
  FFF00000   RO   FFF20000   RO   FFF40000   RO   FFF60000   RO   FFF80000   RO
  FFFA0000   RO   FFFC0000   RO   FFFE0000 E RO   FFFE8000   RO   FFFF0000 E RO
  FFFF8000   RO
=>

The desired env sector is FFF40000->FFF60000, or 0x20000 in length,
just after the 256k u-boot image which starts @ FFF00000.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:

Unable to save the rest of sector (253952)

Allow for 1M malloc pool, the same as used on the sbc8548 board.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

It is just too painful to use interactively without it.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

On signature verification failures fit_image_verify() should
exit with error.
Signed-off-by: NAndrej Rosano <andrej@inversepath.com>

Used NAND chips requires at least 4-bit error correction, so use BCH8
as it is what kernel uses.
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Acked-by: NJavier Martinez Canillas <javier@osg.samsung.com>

Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: NRyan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: NTom Rini <trini@konsulko.com>

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NRyan Harkin <ryan.harkin@linaro.org>
Tested-by: NRyan Harkin <ryan.harkin@linaro.org>

The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.

For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.

In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.

Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: NTom Rini <trini@konsulko.com>

SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.

To illustrate the problem:

Copying data from PC to DFU device
Download    [=========================] 100%       478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!

In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.

478208  = 7 entire sectors of 64kiB + 19456 bytes.

Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.

Fix the issue by always erasing with the erase sector size.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>

- Add deletions from August 30 2015.
- A few from Sept 12, one from Oct 2nd.
Signed-off-by: NTom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.

This reverts commit 653600a7.
Signed-off-by: NTom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config.  To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.

This reverts commit 1363740e.

Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

Add in the commit IDs / dates for boards removed on Sept 2nd.
Signed-off-by: NTom Rini <trini@konsulko.com>

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Signed-off-by: NLubomir Rintel <lkundrak@v3.sk>

The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device.  This patch moves the environment to a higher address to avoid
that.
Signed-off-by: NEric Cooper <ecc@cmu.edu>

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: NVitaly Andrianov <vitalya@ti.com>
Tested-by: NVitaly Andrianov <vitalya@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.
Tested-by: NJoakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: NTom Rini <trini@konsulko.com>

We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cec
(vf610: refactor DDRMC code).
Signed-off-by: NAnthony Felice <tony.felice@timesys.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>

Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.

(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)

Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU  and later causes a PCIE VA access
failure.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>