- 16 7月, 2014 2 次提交
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由 Shengzhou Liu 提交于
Add support for 3rd and 4th I2C. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Heiko Schocher 提交于
If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: NHeiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com>
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- 10 7月, 2014 2 次提交
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由 Felipe Balbi 提交于
Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: NFelipe Balbi <balbi@ti.com>
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由 Felipe Balbi 提交于
some boards won't work if the PHY isn't explicitly powered up. Signed-off-by: NFelipe Balbi <balbi@ti.com>
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- 08 7月, 2014 8 次提交
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由 Dirk Eibach 提交于
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
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由 Dirk Eibach 提交于
IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
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由 Vasili Galka 提交于
get_sclk() was not defined in bfin_wdt.c, include the corresponding header. Cc: Sonic Zhang <sonic.adi@gmail.com> Signed-off-by: NVasili Galka <vvv444@gmail.com>
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由 Masahiro Yamada 提交于
This board is old enough and has no maintainer. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
This board is old enough and has no maintainer. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
These boards are old enough and have no maintainers. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Jeroen Hofstee 提交于
clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Masahiro Yamada 提交于
The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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- 05 7月, 2014 3 次提交
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由 Chin Liang See 提交于
To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Sergey Kostanbaev 提交于
This patch returns back support for old ep93xx processors family Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
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由 Axel Lin 提交于
In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NVipin Kumar <vipin.kumar@st.com> Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>
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- 03 7月, 2014 5 次提交
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由 J. German Rivera 提交于
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com> Signed-off-by: NShruti Kanetkar <Shruti@Freescale.com>
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由 York Sun 提交于
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 Stephen Warren 提交于
Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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由 Stephen Warren 提交于
The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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由 Stephen Warren 提交于
I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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- 02 7月, 2014 8 次提交
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由 Stephen Warren 提交于
Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and "ci_ep" for a struct ci_ep. This is nice and consistent, and helps people know what type a variable is without searching for the declaration. handle_ep_complete() doesn't do this, so fix it to be consistent. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
A UDC's alloc_request method should zero out the newly allocated request. Ensure the Atmel driver does so. This issue was found by code inspection, following the investigation of an intermittent issue with ci_udc, which was tracked down to failing to zero out allocated requests following some of my changes. All other UDC drivers already zero out requests in one way or another. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
struct ci_req is a purely software structure, and needs no specific memory alignment. Hence, allocate it with calloc() rather than memalign(). The use of memalign() was left-over from when struct ci_req was going to hold the aligned bounce buffer, but this is now dynamically allocated. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
There's no need to store an array of QTD pointers in the controller. Since the calculation is so simple, just have ci_get_qtd() perform it at run-time, rather than pre-calculating everything. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
2 QTDs are allocated for each EP. The current allocation scheme aligns the first QTD in each pair, but simply adds the struct size to calculate the second QTD's address. This will result in a non-cache-aligned addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the size of struct ept_queue_item). Similarly, the original ilist_ent_sz calculation aligned the value to ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment requirement into account. This doesn't cause a practical issue unless ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may as well fix the code to be explicit, so it's obviously completely correct. The new value of ILIST_ENT_SZ takes all alignment requirements into account, so we can simplify ci_{flush,invalidate}_qtd() by simply using that macro rather than calling roundup(). Similarly, the calculation of controller.items[i] can be simplified, since each QTD is evenly spaced at its individual alignment requirement, rather than each pair being aligned, and entries within the pair being spaced apart only by structure size. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly call ci_get_qtd() to find the address of the other QTD to use. This will allow us to correctly align each QTD individually in the future, which may involve leaving a gap between the QTDs. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After each pair has been initialized, the pair is cache-flushed. The conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index [0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields the QH/QTD index of the first entry in the pair) rather than dividing by two (which scales the range). Fix this. On my system, this avoids cache debug prints due to requests to flush unaligned ranges. This is caused because the flush calls happen before the items[] array entries are initialized for all but EP0. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 26 6月, 2014 10 次提交
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由 Ilya Ledvich 提交于
Add LAN9500A product ID (0x9e00) in order to support LAN9500A based dongles. Tested on cm_t335. Signed-off-by: NIlya Ledvich <ilya@compulab.co.il> Acked-by: NMarek Vasut <marex@denx.de>
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由 Jeroen Hofstee 提交于
cb_getvar tries to prevent overflowing the response buffer by using strncat. But strncat takes the number of data bytes copied as a limit not the total buffer length so it can still overflow. Pass the correct value instead. cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> cc: Rob Herring <robh@kernel.org> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Jeroen Hofstee 提交于
Because of the brackets the & and && is evaluated before the comparison. This is likely not the intention. Change it to test the first and second condition to both be true. cc: Marek Vasut <marex@denx.de> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Jeroen Hofstee 提交于
since ALLOC_CACHE_ALIGN_BUFFER defines a pointer and not a buffer, the memset with sizeof(rqt) likely does something else then intended. Since there is a memcpy directly after it with the full size, drop the memset completely. Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Acked-by: NLukasz Majewski <l.majewski@samsung.com>
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由 Jeroen Hofstee 提交于
Since the struct fsg_common is calloced, reset it completely with zero's when reused. While at it, make checkpatch happy. cc: Lukasz Majewski <l.majewski@samsung.com> cc: Piotr Wilczek <p.wilczek@samsung.com> cc: Kyungmin Park <kyungmin.park@samsung.com> cc: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NLukasz Majewski <l.majewski@samsung.com>
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由 Yasuhisa Umano 提交于
Initialization of r8a66597 info structure is not enough. Because initilization was used size of pointer. This fixes that use size of r8a6659 info structure. Signed-off-by: NYasuhisa Umano <yasuhisa.umano.zc@renesas.com>
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由 yasuhisa umano 提交于
This driver is processed as two USB hub despite one. The number of root hub is defined in R8A66597_MAX_ROOT_HUB. This fixes that register is accessed by using the definition of R8A66597_MAX_ROOT_HUB. Signed-off-by: NYasuhisa Umano <yasuhisa.umano.zc@renesas.com>
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由 Jeroen Hofstee 提交于
For plain array const can be either before or after the type definition. Adding both is simply redundand. Remove the later one. cc: marex@denx.de Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Stephen Warren 提交于
s/ot/to/ Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
ci_udc.c's usb_gadget_unregister_driver() doesn't call driver->unbind() unlike other USB gadget drivers. Fix it to do this. Without this, when ether.c's CDC Ethernet device is torn down, eth_unbind() is never called, so dev->gadget is never set to NULL. For some reason, usb_eth_halt() is called both at the end of the first use of the Ethernet device, and prior to any subsequent use. Since dev->gadget is never cleared, all calls to usb_eth_halt() attempt to stop, disconnect, and clean up the device, resulting in double cleanup, which hangs U-Boot on my Tegra device at least. ci_udc allocates its own singleton EP0 request object, and cleans it up during usb_gadget_unregister_driver(). This appears necessary when using the USB gadget framework in U-Boot, since that does not allocate/free the EP0 request. However, the CDC Ethernet driver *does* allocate and free its own EP0 requests. Consequently, we must protect ci_ep_free_request() against double-freeing the request. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 23 6月, 2014 2 次提交
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由 Jeroen Hofstee 提交于
Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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