- 16 10月, 2007 1 次提交
-
-
- 15 10月, 2007 2 次提交
-
-
由 Stefan Roese 提交于
The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: NStefan Roese <sr@denx.de>
-
- 14 10月, 2007 12 次提交
-
-
由 Michal Simek 提交于
and remove code violation
-
-
由 Michal Simek 提交于
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
由 Wolfgang Denk 提交于
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NWolfgang Denk <wd@denx.de>
-
-
-
-
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
-
- 12 10月, 2007 1 次提交
-
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
- 10 10月, 2007 3 次提交
-
-
由 Wolfgang Denk 提交于
-
由 Wolfgang Denk 提交于
-
由 Wolfgang Denk 提交于
-
- 09 10月, 2007 1 次提交
-
-
由 Grzegorz Bernacki 提交于
Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
-
- 07 10月, 2007 1 次提交
-
-
由 Haavard Skinnemoen 提交于
The ATSTK1000-specific flash driver intializes bi_flashstart, bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI driver, don't. Initialize these in board_init_r instead so that things will still be set up correctly when we switch to the CFI driver. Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
-
- 05 10月, 2007 2 次提交
-
-
由 Marian Balakowicz 提交于
Signed-off-by: NMarian Balakowicz <m8@semihalf.com>
-
由 Bartlomiej Sieka 提交于
Signed-off-by: NBartlomiej Sieka <tur@semihalf.com>
-
- 04 10月, 2007 1 次提交
-
-
- 03 10月, 2007 2 次提交
-
-
由 Haavard Skinnemoen 提交于
CFG_MEMTEST_START uses weird magic involving gd, which fails to compile. Use hardcoded values instead (we actually know how much RAM we have on board.) Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
-
由 Haavard Skinnemoen 提交于
-
- 02 10月, 2007 5 次提交
-
-
-
由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Grzegorz Bernacki 提交于
EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>
-
由 Timo Ketola 提交于
Original isp116x-hcd code prepared multiple PTDs for longer than 16 byte transfers for one endpoint. That is unnecessary because the ISP116x is able to split long data from one PTD into multiple transactions based on the buffer size of the endpoint. It also caused serious problems if the endpoint NAKed some of the transactions. In that case ISP116x wouldn't notice that the other PTDs were for the same endpoint and would try the other PTDs possibly out of order. That would break the whole transfer. This patch makes isp116x_submit_job to use one PTD for one transfer. Signed-off-by: NTimo Ketola <timo.ketola@exertus.fi> Signed-off-by: NMarkus Klotzbuecher <mk@denx.de>
-
- 28 9月, 2007 1 次提交
-
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
- 27 9月, 2007 2 次提交
-
-
由 Stefan Roese 提交于
-
由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
-
- 26 9月, 2007 2 次提交
-
-
-
由 Grant Likely 提交于
CFG_FPGA_XILINX is a bit value used to test against the value in CONFIG_FPGA. Testing for a value will always return TRUE. I don't think that is the intention in this code. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
-
- 24 9月, 2007 4 次提交
-
-
由 Michal Simek 提交于
-
由 Michal Simek 提交于
because changing of command handling brings compilation problems
-
由 Michal Simek 提交于
Both codes are written by myself without any support from CTU
-
由 Michal Simek 提交于
because PowerPC 405 can use UartLite as console
-