Merge git://www.denx.de/git/u-boot

Makefile

 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@
 VERSION = 1
 PATCHLEVEL = 3
 SUBLEVEL = 0
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -211,6 +211,7 @@ LIBS += drivers/libdrivers.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/onenand/libonenand.a
 LIBS += drivers/net/libnet.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a

board/amcc/luan/luan.c

@@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  ************************************************************************/
 int board_early_init_f(void)
 {
-	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
 	mtebc( pb0ap,  0x03800000 );	/* set chip selects */
 	mtebc( pb0cr,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
 	mtebc( pb1ap,  0x03800000 );
@@ -66,8 +64,6 @@ int board_early_init_f(void)
 	mtdcr( uic0sr, 0x00000000 );	/* clear all interrupts */
 	mtdcr( uic0sr, 0xffffffff );
 
-	x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
 	return  0;
 }
 
@@ -79,7 +75,18 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-	x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+	/* set modes of operation */
+	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+		EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+	/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+	x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+	/* put Ethernet+PHY in reset */
+	x->ethuart &= ~EPLD2_RESET_ETH_N;
+	udelay(10000);
+	/* take Ethernet+PHY out of reset */
+	x->ethuart |= EPLD2_RESET_ETH_N;
 
 	return  0;
 }

board/at91rm9200dk/led.c

@@ -66,7 +66,7 @@ void	red_LED_off(void)
 }
 
 
-void LED_init (void)
+void coloured_LED_init (void)
 {
 	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
 	AT91PS_PMC	PMC	= AT91C_BASE_PMC;

board/atmel/atstk1000/flash.c

@@ -55,10 +55,6 @@ unsigned long flash_init(void)
 	unsigned long addr;
 	unsigned int i;
 
-	gd->bd->bi_flashstart = CFG_FLASH_BASE;
-	gd->bd->bi_flashsize = CFG_FLASH_SIZE;
-	gd->bd->bi_flashoffset = _edata - _text;
-
 	flash_info[0].size = CFG_FLASH_SIZE;
 	flash_info[0].sector_count = 135;
 

board/cm5200/cm5200.c

@@ -397,6 +397,7 @@ int misc_init_r(void)
 					"operational\n");
 
 	/* set the hostname appropriate to the module we're running on */
+	hostname[0] = 0x00;
 	compose_hostname(hw_id, hostname);
 	setenv("hostname", hostname);
 

board/mpl/vcma9/vcma9.c

@@ -288,7 +288,7 @@ int dram_init(void)
 
 int checkboard(void)
 {
-	unsigned char s[50];
+	char s[50];
 	int i;
 	backup_t *b = (backup_t *) s;
 
@@ -337,7 +337,7 @@ int overwrite_console(void)
 ************************************************************************/
 void print_vcma9_info(void)
 {
-	unsigned char s[50];
+	char s[50];
 	int i;
 
 	if ((i = getenv_r("serial#", s, 32)) < 0) {

common/Makefile

@@ -37,13 +37,14 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  cmd_load.o cmd_log.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
+	  cmd_onenand.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
 	  cmd_universe.o cmd_usb.o cmd_vfd.o \
 	  command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
-	  env_nvram.o env_nowhere.o \
+	  env_onenand.o env_nvram.o env_nowhere.o \
 	  exports.o \
 	  fdt_support.o flash.o fpga.o ft_build.o \
 	  hush.o kgdb.o lcd.o lists.o lynxkdi.o \

common/cmd_fpga.c

@@ -60,6 +60,7 @@ static int fpga_get_op (char *opstr);
 /* Convert bitstream data and load into the fpga */
 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 {
+#if (CONFIG_FPGA & CFG_FPGA_XILINX)
 	unsigned int length;
 	unsigned char* swapdata;
 	unsigned int swapsize;
@@ -72,7 +73,6 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
 
 	dataptr = (unsigned char *)fpgadata;
 
-#if CFG_FPGA_XILINX
 	/* skip the first bytes of the bitsteam, their meaning is unknown */
 	length = (*dataptr << 8) + *(dataptr+1);
 	dataptr+=2;

common/cmd_mfsl.c

@@ -355,19 +355,18 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	unsigned int reg = 0;
 	unsigned int val = 0;
 
-	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
-	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
-	if (argc < 1) {
+	if (argc < 2) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
+	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
 	switch (reg) {
 	case 0x1:
 		if (argc > 2) {
 			MTS (val, rmsr);
 			NOP;
 			MFS (val, rmsr);
-
 		} else {
 			MFS (val, rmsr);
 		}
@@ -382,6 +381,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		puts ("ESR");
 		break;
 	default:
+		puts ("Unsupported register\n");
 		return 1;
 	}
 	printf (": 0x%08lx\n", val);
@@ -408,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 		" 3 - blocking control write\n");
 
 U_BOOT_CMD (rspr, 3, 1, do_rspr,
-		"rmsr    - read/write special purpose register\n",
+		"rspr    - read/write special purpose register\n",
 		"- reg_num [write value] read/write special purpose register\n"
-		" 0 - MSR - Machine status register\n"
-		" 1 - EAR - Exception address register\n"
-		" 2 - ESR - Exception status register\n");
+		" 1 - MSR - Machine status register\n"
+		" 3 - EAR - Exception address register\n"
+		" 5 - ESR - Exception status register\n");
 
 #endif

common/cmd_nvedit.c

@@ -57,8 +57,9 @@ DECLARE_GLOBAL_DATA_PTR;
     !defined(CFG_ENV_IS_IN_FLASH)	&& \
     !defined(CFG_ENV_IS_IN_DATAFLASH)	&& \
     !defined(CFG_ENV_IS_IN_NAND)	&& \
+    !defined(CFG_ENV_IS_IN_ONENAND)	&& \
     !defined(CFG_ENV_IS_NOWHERE)
-# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
+# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
 #endif
 
 #define XMK_STR(x)	#x
@@ -553,7 +554,8 @@ int getenv_r (char *name, char *buf, unsigned len)
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
 int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern char * env_name_spec;
@@ -608,7 +610,8 @@ U_BOOT_CMD(
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \
     || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \
-    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND))
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \
+    || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))
 U_BOOT_CMD(
 	saveenv, 1, 0,	do_saveenv,
 	"saveenv - save environment variables to persistent storage\n",

common/cmd_onenand.c

+/*
+ *  U-Boot command for OneNAND support
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int ret = 0;
+
+	switch (argc) {
+	case 0:
+	case 1:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+
+	case 2:
+		if (strncmp(argv[1], "open", 4) == 0) {
+			onenand_init();
+			return 0;
+		}
+		onenand_print_device_info(onenand_chip.device_id, 1);
+		return 0;
+
+	default:
+		/* At least 4 args */
+		if (strncmp(argv[1], "erase", 5) == 0) {
+			struct erase_info instr;
+			ulong start, end;
+			ulong block;
+
+			start = simple_strtoul(argv[2], NULL, 10);
+			end = simple_strtoul(argv[3], NULL, 10);
+			start -= (unsigned long)onenand_chip.base;
+			end -= (unsigned long)onenand_chip.base;
+
+			if (!end || end < 0)
+				end = start;
+
+			printf("Erase block from %d to %d\n", start, end);
+
+			for (block = start; block <= end; block++) {
+				instr.addr = block << onenand_chip.erase_shift;
+				instr.len = 1 << onenand_chip.erase_shift;
+				ret = onenand_erase(&onenand_mtd, &instr);
+				if (ret) {
+					printf("erase failed %d\n", block);
+					break;
+				}
+			}
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "read", 4) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong ofs = simple_strtoul(argv[3], NULL, 16);
+			size_t len = simple_strtoul(argv[4], NULL, 16);
+			size_t retlen = 0;
+			int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1;
+
+			ofs -= (unsigned long)onenand_chip.base;
+
+			if (oob)
+				onenand_read_oob(&onenand_mtd, ofs, len,
+						 &retlen, (u_char *) addr);
+			else
+				onenand_read(&onenand_mtd, ofs, len, &retlen,
+					     (u_char *) addr);
+			printf("Done\n");
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "write", 5) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong ofs = simple_strtoul(argv[3], NULL, 16);
+			size_t len = simple_strtoul(argv[4], NULL, 16);
+			size_t retlen = 0;
+
+			ofs -= (unsigned long)onenand_chip.base;
+
+			onenand_write(&onenand_mtd, ofs, len, &retlen,
+				      (u_char *) addr);
+			printf("Done\n");
+
+			return 0;
+		}
+
+		if (strncmp(argv[1], "block", 5) == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong block = simple_strtoul(argv[3], NULL, 10);
+			ulong page = simple_strtoul(argv[4], NULL, 10);
+			size_t len = simple_strtol(argv[5], NULL, 10);
+			size_t retlen = 0;
+			ulong ofs;
+			int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1;
+
+			ofs = block << onenand_chip.erase_shift;
+			if (page)
+				ofs += page << onenand_chip.page_shift;
+
+			if (!len) {
+				if (oob)
+					len = 64;
+				else
+					len = 512;
+			}
+
+			if (oob)
+				onenand_read_oob(&onenand_mtd, ofs, len,
+						 &retlen, (u_char *) addr);
+			else
+				onenand_read(&onenand_mtd, ofs, len, &retlen,
+					     (u_char *) addr);
+			return 0;
+		}
+
+		break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	onenand,	6,	1,	do_onenand,
+	"onenand - OneNAND sub-system\n",
+	"info   - show available OneNAND devices\n"
+	"onenand read[.oob] addr ofs len - read data at ofs with len to addr\n"
+	"onenand write addr ofs len - write data at ofs with len from addr\n"
+	"onenand erase saddr eaddr - erase block start addr to end addr\n"
+	"onenand block[.oob] addr block [page] [len] - "
+		"read data with (block [, page]) to addr"
+);
+
+#endif /* CONFIG_CMD_ONENAND */

common/env_onenand.c

+/*
+ * (C) Copyright 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_ONENAND)	/* Environment is in OneNAND */
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* References to names in env_common.c */
+extern uchar default_environment[];
+
+#define ONENAND_ENV_SIZE(mtd)	(mtd.oobblock - ENV_HEADER_SIZE)
+
+char *env_name_spec = "OneNAND";
+
+#ifdef ENV_IS_EMBEDDED
+extern uchar environment[];
+env_t *env_ptr = (env_t *) (&environment[0]);
+#else /* ! ENV_IS_EMBEDDED */
+static unsigned char onenand_env[MAX_ONENAND_PAGESIZE];
+env_t *env_ptr = (env_t *) onenand_env;
+#endif /* ENV_IS_EMBEDDED */
+
+uchar env_get_char_spec(int index)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return (*((uchar *) (gd->env_addr + index)));
+}
+
+void env_relocate_spec(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long env_addr;
+	int use_default = 0;
+	int retlen;
+
+	env_addr = CFG_ENV_ADDR;
+	env_addr -= (unsigned long)onenand_chip.base;
+
+	/* Check OneNAND exist */
+	if (onenand_mtd.oobblock)
+		/* Ignore read fail */
+		onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock,
+			     &retlen, (u_char *) env_ptr);
+	else
+		onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE;
+
+	if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) !=
+	    env_ptr->crc)
+		use_default = 1;
+
+	if (use_default) {
+		memcpy(env_ptr->data, default_environment,
+		       ONENAND_ENV_SIZE(onenand_mtd));
+		env_ptr->crc =
+		    crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd));
+	}
+
+	gd->env_addr = (ulong) & env_ptr->data;
+	gd->env_valid = 1;
+}
+
+int saveenv(void)
+{
+	unsigned long env_addr = CFG_ENV_ADDR;
+	struct erase_info instr;
+	int retlen;
+
+	instr.len = CFG_ENV_SIZE;
+	instr.addr = env_addr;
+	instr.addr -= (unsigned long)onenand_chip.base;
+	if (onenand_erase(&onenand_mtd, &instr)) {
+		printf("OneNAND: erase failed at 0x%08x\n", env_addr);
+		return 1;
+	}
+
+	/* update crc */
+	env_ptr->crc =
+	    crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE);
+
+	env_addr -= (unsigned long)onenand_chip.base;
+	if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen,
+	     (u_char *) env_ptr)) {
+		printf("OneNAND: write failed at 0x%08x\n", instr.addr);
+		return 2;
+	}
+
+	return 0;
+}
+
+int env_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* use default */
+	gd->env_addr = (ulong) & default_environment[0];
+	gd->env_valid = 1;
+
+	return 0;
+}
+
+#endif /* CFG_ENV_IS_IN_ONENAND */

cpu/arm720t/serial.c

@@ -125,6 +125,8 @@ serial_puts (const char *s)
 
 #elif defined(CONFIG_LPC2292)
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #include <asm/arch/hardware.h>
 
 void serial_setbrg (void)

cpu/arm920t/start.S

@@ -27,9 +27,7 @@
 
 #include <config.h>
 #include <version.h>
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-#include	<led.h>
-#endif
+#include <status_led.h>
 
 /*
  *************************************************************************
@@ -41,7 +39,7 @@
 
 
 .globl _start
-_start:	b       reset
+_start:	b       start_code
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -64,7 +62,7 @@ _fiq:			.word fiq
 /*
  *************************************************************************
  *
- * Startup Code (reset vector)
+ * Startup Code (called from the ARM reset exception vector)
  *
  * do important init only if we don't start from memory!
  * relocate armboot to ram
@@ -106,10 +104,10 @@ FIQ_STACK_START:
 
 
 /*
- * the actual reset code
+ * the actual start code
  */
 
-reset:
+start_code:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -118,58 +116,12 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#if	CONFIG_AT91RM9200
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-	bl LED_init
+	bl coloured_LED_init
 	bl red_LED_on
-#endif
 
-#ifdef CONFIG_BOOTBINFUNC
-/* code based on entry.S from ATMEL */
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-	/* Get the CKGR Base Address */
-	ldr     r1, =AT91C_BASE_CKGR
-
-/* Main oscillator Enable register	APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
-/*	ldr 	r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
-	ldr 	r0, =0x0000FF01
-	str     r0, [r1, #CKGR_MOR]
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr 	r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-	/* scratch stack */
-	ldr 	r1, =0x00204000
-	/* Insure word alignment */
-	bic     r1, r1, #3
-	/* Init stack SYS	 */
-	mov     sp, r1
-	/*
-	 * This does a lot more than just set up the memory, which
-	 * is why it's called lowlevelinit
-	 */
-	bl	lowlevelinit /* in memsetup.S */
-	bl	icache_enable;
-	/* ------------------------------------
-	 * Read/modify/write CP15 control register
-	 * -------------------------------------
-	 * read cp15 control register (cp15 r1) in r0
-	 * ------------------------------------
-	 */
-	mrc     p15, 0, r0, c1, c0, 0
-	/* Reset bit :Little Endian end fast bus mode */
-	ldr     r3, =0xC0000080
-	/* Set bit :Asynchronous clock mode, Not Fast Bus */
-	ldr     r4, =0xC0000000
-	bic     r0, r0, r3
-	orr     r0, r0, r4
-	/* write r0 in cp15 control register (cp15 r1) */
-	mcr     p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_BOOTBINFUNC */
+#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
 	/*
-	 * relocate exeception table
+	 * relocate exception table
 	 */
 	ldr	r0, =_start
 	ldr	r1, =0x0
@@ -181,19 +133,20 @@ copyex:
 	bne	copyex
 #endif
 
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON		0x15300000
-# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
-# define CLKDIVN	0x14800014	/* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON		0x53000000
-# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
-# define INTSUBMSK	0x4A00001C
-# define CLKDIVN	0x4C000014	/* clock divisor register */
-#endif
-
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+	/* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+#  define pWTCON		0x15300000
+#  define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+#  define CLKDIVN	0x14800014	/* clock divisor register */
+#else
+#  define pWTCON		0x53000000
+#  define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#  define INTSUBMSK	0x4A00001C
+#  define CLKDIVN	0x4C000014	/* clock divisor register */
+# endif
+
 	ldr     r0, =pWTCON
 	mov     r1, #0x0
 	str     r1, [r0]
@@ -226,25 +179,7 @@ copyex:
 #endif
 
 #ifdef	CONFIG_AT91RM9200
-#ifdef CONFIG_BOOTBINFUNC
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
 
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
-#else
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
@@ -284,27 +219,6 @@ clbss_l:str	r2, [r0]		/* clear loop...                    */
 	cmp	r0, r1
 	ble	clbss_l
 
-#if 0
-	/* try doing this stuff after the relocation */
-	ldr     r0, =pWTCON
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMR
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-	/* END stuff after relocation */
-#endif
-
 	ldr	pc, _start_armboot
 
 _start_armboot:	.word start_armboot

cpu/microblaze/cache.c

 /*
  * (C) Copyright 2007 Michal Simek
  *
- * Michal SIMEK <moonstr@monstr.eu>
+ * Michal SIMEK <monstr@monstr.eu>
  *
  * See file CREDITS for list of people who contributed to this
  * project.

cpu/microblaze/start.S

@@ -33,15 +33,13 @@ _start:
 	addi	r1, r0, CFG_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 	/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
-	addi	r6, r0, 0xb000	/* hex b000 opcode imm */
-	bslli	r6, r6, 16	/* shift */
+	addi	r6, r0, 0xb0000000	/* hex b000 opcode imm */
 	swi	r6, r0, 0x0	/* reset address */
 	swi	r6, r0, 0x8	/* user vector exception */
 	swi	r6, r0, 0x10	/* interrupt */
 	swi	r6, r0, 0x20	/* hardware exception */
 
-	addi	r6, r0, 0xb808	/* hew b808 opcode brai*/
-	bslli	r6, r6, 16
+	addi	r6, r0, 0xb8080000	/* hew b808 opcode brai*/
 	swi	r6, r0, 0x4	/* reset address */
 	swi	r6, r0, 0xC	/* user vector exception */
 	swi	r6, r0, 0x14	/* interrupt */

cpu/microblaze/timer.c

@@ -33,10 +33,17 @@ void reset_timer (void)
 	timestamp = 0;
 }
 
+#ifdef CFG_TIMER_0
 ulong get_timer (ulong base)
 {
 	return (timestamp - base);
 }
+#else
+ulong get_timer (ulong base)
+{
+	return (timestamp++ - base);
+}
+#endif
 
 void set_timer (ulong t)
 {

cpu/ppc4xx/440spe_pcie.c

@@ -104,7 +104,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
 	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
 		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
 		return 0;
-		
+
 	address = pcie_get_base(hose, devfn);
 	offset += devfn << 4;
 
@@ -136,12 +136,12 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 	int offset, int len, u32 val) {
 
 	u8 *address;
-	
+
 	/*
 	 * Bus numbers are relative to hose->first_busno
 	 */
 	devfn -= PCI_BDF(hose->first_busno, 0, 0);
-	
+
 	/*
 	 * Same constraints as in pcie_read_config().
 	 */
@@ -151,7 +151,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 	if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
 		((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
 		return 0;
-	
+
 	address = pcie_get_base(hose, devfn);
 	offset += devfn << 4;
 
@@ -926,7 +926,7 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 		 in_le16((u16 *)(mbase + PCI_COMMAND)) |
 		 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	printf("PCIE:%d successfully set as rootpoint\n",port);
-	
+
 	/* Set Device and Vendor Id */
 	switch (port) {
 	case 0:

cpu/ppc4xx/4xx_enet.c

@@ -138,7 +138,8 @@
 #define BI_PHYMODE_MII   7
 #endif
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+	defined(CONFIG_440GRX) || defined(CONFIG_440SP)
 #define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
 #endif
 
@@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	int ethgroup = -1;
 #endif
 #endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long mfr;
 #endif
 
@@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	__asm__ volatile ("eieio");
 
 	/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
 	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	if (failsafe <= 0)
 		printf("\nProblem resetting EMAC!\n");
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
 	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -920,8 +924,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	/* set speed */
 	if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 		unsigned long pfc1;
 
 		mfsdr (sdr_pfc1, pfc1);

cpu/pxa/mmc.c

@@ -438,11 +438,11 @@ mmc_init(int verbose)
 		/* FIXME fill in the correct size (is set to 32MByte) */
 		mmc_dev.blksz = 512;
 		mmc_dev.lba = 0x10000;
-		sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+		sprintf((char*)mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
 				cid->id[0], cid->id[1], cid->id[2],
 				cid->sn[0], cid->sn[1], cid->sn[2]);
-		sprintf(mmc_dev.product,"%s",cid->name);
-		sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+		sprintf((char*)mmc_dev.product,"%s",cid->name);
+		sprintf((char*)mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
 		mmc_dev.removable = 0;
 		mmc_dev.block_read = mmc_bread;
 

drivers/onenand/Makefile

+#
+# Copyright (C) 2005-2007 Samsung Electronics.
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)libonenand.a
+
+COBJS	:= onenand_base.o onenand_bbt.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

drivers/onenand/onenand_bbt.c

+/*
+ *  linux/drivers/mtd/onenand/onenand_bbt.c
+ *
+ *  Bad Block Table support for the OneNAND driver
+ *
+ *  Copyright(c) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  TODO:
+ *    Split BBT core and chip specific BBT.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <malloc.h>
+
+#include <asm/errno.h>
+
+/**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @param buf		the buffer to search
+ * @param len		the length of buffer to search
+ * @param paglen	the pagelength
+ * @param td		search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check and the pattern is expected to start
+ * at offset 0.
+ */
+static int check_short_pattern(uint8_t * buf, int len, int paglen,
+			       struct nand_bbt_descr *td)
+{
+	int i;
+	uint8_t *p = buf;
+
+	/* Compare the pattern */
+	for (i = 0; i < td->len; i++) {
+		if (p[i] != td->pattern[i])
+			return -1;
+	}
+	return 0;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @param mtd		MTD device structure
+ * @param buf		temporary buffer
+ * @param bd		descriptor for the good/bad block search pattern
+ * @param chip		create the table for a specific chip, -1 read all chips.
+ *              Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static int create_bbt(struct mtd_info *mtd, uint8_t * buf,
+		      struct nand_bbt_descr *bd, int chip)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int i, j, numblocks, len, scanlen;
+	int startblock;
+	loff_t from;
+	size_t readlen, ooblen;
+
+	printk(KERN_INFO "Scanning device for bad blocks\n");
+
+	len = 1;
+
+	/* We need only read few bytes from the OOB area */
+	scanlen = ooblen = 0;
+	readlen = bd->len;
+
+	/* chip == -1 case only */
+	/* Note that numblocks is 2 * (real numblocks) here;
+	 * see i += 2 below as it makses shifting and masking less painful
+	 */
+	numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+	startblock = 0;
+	from = 0;
+
+	for (i = startblock; i < numblocks;) {
+		int ret;
+
+		for (j = 0; j < len; j++) {
+			size_t retlen;
+
+			/* No need to read pages fully,
+			 * just read required OOB bytes */
+			ret = onenand_read_oob(mtd,
+					     from + j * mtd->oobblock +
+					     bd->offs, readlen, &retlen,
+					     &buf[0]);
+
+			if (ret && ret != -EAGAIN) {
+				printk("ret = %d\n", ret);
+				return ret;
+			}
+
+			if (check_short_pattern
+			    (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+				bbm->bbt[i >> 3] |= 0x03 << (i & 0x6);
+				printk(KERN_WARNING
+				       "Bad eraseblock %d at 0x%08x\n", i >> 1,
+				       (unsigned int)from);
+				break;
+			}
+		}
+		i += 2;
+		from += (1 << bbm->bbt_erase_shift);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+ */
+static inline int onenand_memory_bbt(struct mtd_info *mtd,
+				     struct nand_bbt_descr *bd)
+{
+	unsigned char data_buf[MAX_ONENAND_PAGESIZE];
+
+	bd->options &= ~NAND_BBT_SCANEMPTY;
+	return create_bbt(mtd, data_buf, bd, -1);
+}
+
+/**
+ * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad
+ * @param mtd		MTD device structure
+ * @param offs		offset in the device
+ * @param allowbbt	allow access to bad block table region
+ */
+static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int block;
+	uint8_t res;
+
+	/* Get block number * 2 */
+	block = (int)(offs >> (bbm->bbt_erase_shift - 1));
+	res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+	DEBUG(MTD_DEBUG_LEVEL2,
+	      "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+	      (unsigned int)offs, block >> 1, res);
+
+	switch ((int)res) {
+	case 0x00:
+		return 0;
+	case 0x01:
+		return 1;
+	case 0x02:
+		return allowbbt ? 0 : 1;
+	}
+
+	return 1;
+}
+
+/**
+ * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s)
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the onenand_free_bbt function.
+ *
+ */
+int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int len, ret = 0;
+
+	len = mtd->size >> (this->erase_shift + 2);
+	/* Allocate memory (2bit per block) */
+	bbm->bbt = malloc(len);
+	if (!bbm->bbt) {
+		printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+		return -ENOMEM;
+	}
+	/* Clear the memory bad block table */
+	memset(bbm->bbt, 0x00, len);
+
+	/* Set the bad block position */
+	bbm->badblockpos = ONENAND_BADBLOCK_POS;
+
+	/* Set erase shift */
+	bbm->bbt_erase_shift = this->erase_shift;
+
+	if (!bbm->isbad_bbt)
+		bbm->isbad_bbt = onenand_isbad_bbt;
+
+	/* Scan the device to build a memory based bad block table */
+	if ((ret = onenand_memory_bbt(mtd, bd))) {
+		printk(KERN_ERR
+		       "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n");
+		free(bbm->bbt);
+		bbm->bbt = NULL;
+	}
+
+	return ret;
+}
+
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern,
+};
+
+/**
+ * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device
+ * @param mtd		MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the onenand_scan_bbt function
+ */
+int onenand_default_bbt(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm;
+
+	this->bbm = malloc(sizeof(struct bbm_info));
+	if (!this->bbm)
+		return -ENOMEM;
+
+	bbm = this->bbm;
+
+	memset(bbm, 0, sizeof(struct bbm_info));
+
+	/* 1KB page has same configuration as 2KB page */
+	if (!bbm->badblock_pattern)
+		bbm->badblock_pattern = &largepage_memorybased;
+
+	return onenand_scan_bbt(mtd, bbm->badblock_pattern);
+}
+
+#endif /* CFG_CMD_ONENAND */

drivers/serial_xuartlite.c

@@ -24,7 +24,7 @@
 
 #include <config.h>
 
-#ifdef	CONFIG_MICROBLAZE
+#ifdef	CONFIG_XILINX_UARTLITE
 
 #include <asm/serial_xuartlite.h>
 

drivers/usb_ohci.c

@@ -93,6 +93,7 @@
 #ifdef CONFIG_PCI_OHCI
 static struct pci_device_id ohci_pci_ids[] = {
 	{0x10b9, 0x5237},	/* ULI1575 PCI OHCI module ids */
+	{0x1033, 0x0035},	/* NEC PCI OHCI module ids */
 	/* Please add supported PCI OHCI controller ids here */
 	{0, 0}
 };

include/asm-avr32/string.h

@@ -23,6 +23,6 @@
 #define __ASM_AVR32_STRING_H
 
 #define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t n);
+extern void *memset(void *s, int c, __kernel_size_t n);
 
 #endif /* __ASM_AVR32_STRING_H */

include/config_cmd_all.h

@@ -59,6 +59,7 @@
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 #define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_ONENAND	/* OneNAND support		*/
 #define CONFIG_CMD_PCI		/* pciinfo			*/
 #define CONFIG_CMD_PCMCIA	/* PCMCIA support		*/
 #define CONFIG_CMD_PING		/* ping support			*/
@@ -76,6 +77,6 @@
 #define CONFIG_CMD_USB		/* USB Support			*/
 #define CONFIG_CMD_VFD		/* VFD support (TRAB)		*/
 #define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
-#define CONFIG_CMD_MUX		/* AT91 MMC/SPI Mux Support     */
+#define CONFIG_CMD_AT91_SPIMUX	/* AT91 MMC/SPI Mux Support     */
 
 #endif	/* _CONFIG_CMD_ALL_H */

include/configs/TQM5200.h

@@ -188,7 +188,7 @@
 #endif
 
 #ifdef CONFIG_PCI
-#define CONFIG_CMD_CMD_PCI
+#define CONFIG_CMD_PCI
 #endif
 
 #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
@@ -238,13 +238,13 @@
 		"protect on FC000000 +${filesize}\0"
 #endif
 
-#ifndef CONFIG_CAM5200
+#if defined(CONFIG_TQM5200)
 #define CUSTOM_ENV_SETTINGS						\
+	"hostname=tqm5200\0"						\
 	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0"			\
 	"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0"			\
 	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
-#else
+#elif defined(CONFIG_CAM5200)
 #define CUSTOM_ENV_SETTINGS						\
 	"bootfile=cam5200/uImage\0"					\
 	"u-boot=cam5200/u-boot.bin\0"					\
@@ -252,11 +252,13 @@
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	"console=ttyS0\0"						\
-	"kernel_addr=200000\0"						\
-	"fdt_addr=400000\0"						\
-	"hostname=tqm5200\0"						\
 	"netdev=eth0\0"							\
+	"console=ttyPSC0\0"						\
+	"fdt_addr=FC0A0000\0"						\
+	"kernel_addr=FC0C0000\0"					\
+	"ramdisk_addr=FC300000\0"					\
+	"kernel_addr_r=200000\0"					\
+	"fdt_addr_r=400000\0"						\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
@@ -266,16 +268,20 @@
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addcons=setenv bootargs ${bootargs} "				\
 		"console=${console},${baudrate}\0"			\
-	"flash_self=run ramargs addip addcons;"				\
+	"flash_self_old=sete console ttyS0; run ramargs addip addcons;"	\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip addcons;"				\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;"	\
 		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
-		"run nfsargs addip addcons;bootm\0"			\
-	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};"		\
-		"tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;"	\
-		"run nfsargs addip addcons;"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
+		"sete console ttyS0; run nfsargs addip addcons;bootm\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons; "				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	CUSTOM_ENV_SETTINGS						\
 	"load=tftp 200000 ${u-boot}\0"					\
 	ENV_UPDT							\
@@ -408,11 +414,12 @@
 #  endif /* CFG_LOWBOOT */
 # else	/* !CONFIG_TQM5200_B */
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
-						"1408k(kernel),"	\
+						"128k(dtb),"		\
+						"2304k(kernel),"	\
 						"2m(initrd),"		\
 						"4m(small-fs),"		\
 						"8m(misc),"		\
-						"16m(big-fs)"
+						"15m(big-fs)"
 # endif /* CONFIG_TQM5200_B */
 #elif defined (CONFIG_CAM5200)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\

include/configs/ads5121.h

@@ -234,6 +234,14 @@
 #define CFG_I2C_NOPROBES	{{0,0x69}}	* Don't probe these addrs */
 #endif
 
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
+
 /*
  * Ethernet configuration
  */
@@ -275,6 +283,7 @@
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

include/configs/atstk1002.h

@@ -39,8 +39,10 @@
 #define CFG_HZ				1000
 
 /*
- * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
- * frequency and the peripherals to run at 1/4 the PLL frequency.
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
  */
 #define CONFIG_PLL			1
 #define CFG_POWER_MANAGER		1
@@ -48,9 +50,25 @@
 #define CFG_PLL0_DIV			1
 #define CFG_PLL0_MUL			7
 #define CFG_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
 #define CFG_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
 #define CFG_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
 #define CFG_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
 #define CFG_CLKDIV_PBB			1
 
 /*
@@ -78,7 +96,7 @@
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTARGS							\
-	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
+	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
 
 #define CONFIG_BOOTCOMMAND						\
 	"fsload; bootm $(fileaddr)"
@@ -87,7 +105,7 @@
  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  * data on the serial line may interrupt the boot sequence.
  */
-#define CONFIG_BOOTDELAY		2
+#define CONFIG_BOOTDELAY		1
 #define CONFIG_AUTOBOOT			1
 #define CONFIG_AUTOBOOT_KEYED		1
 #define CONFIG_AUTOBOOT_PROMPT				\
@@ -103,8 +121,8 @@
  * generated and assigned to the environment variables "ethaddr" and
  * "eth1addr".
  */
-#define CONFIG_ETHADDR			"6a:87:71:14:cd:cb"
-#define CONFIG_ETH1ADDR			"ca:f8:15:e6:3e:e6"
+#define CONFIG_ETHADDR			6a:87:71:14:cd:cb
+#define CONFIG_ETH1ADDR			ca:f8:15:e6:3e:e6
 #define CONFIG_OVERWRITE_ETHADDR_ONCE	1
 #define CONFIG_NET_MULTI		1
 
@@ -182,12 +200,8 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START						\
-	({ gd->bd->bi_dram[0].start; })
-#define CFG_MEMTEST_END							\
-	({								\
-		gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;	\
-	})
+#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
 #endif /* __CONFIG_H */

include/configs/lwmon5.h

@@ -200,12 +200,13 @@
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
+	"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
+	"flash_self=run ramargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addtty addmisc;bootm\0"		\
 	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
 	"bootfile=/tftpboot/lwmon5/uImage\0"				\
 	"kernel_addr=FC000000\0"					\
@@ -338,7 +339,12 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
 #define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
+#if 0
+/*
+ * ToDo: Watchdog is not test fully, so exclude it for now
+ */
 #define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
+#endif
 
 /*
  * For booting Linux, the board info and command line data
@@ -472,7 +478,7 @@
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\

include/configs/ml401.h

 /*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
  *
- * Michal SIMEK <monstr@seznam.cz>
+ * Michal SIMEK <monstr@monstr.eu>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -32,6 +32,7 @@
 #define	CONFIG_ML401		1	/* ML401 Board */
 
 /* uart */
+#define	CONFIG_XILINX_UARTLITE
 #define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
 #define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
@@ -58,6 +59,7 @@
 #define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
 #define	FREQUENCE		XILINX_CLOCK_FREQ
 #define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
+#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
 
 /* FSL */
 #define	CFG_FSL_2
@@ -86,7 +88,7 @@
  * 0x11FB_F000	CFG_MONITOR_BASE
  *					MONITOR_CODE	256kB	Env
  * 0x13FF_F000	CFG_GBL_DATA_OFFSET
- * 					GLOBAL_DATA	4kB	bd, gd
+ *					GLOBAL_DATA	4kB	bd, gd
  * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  */
 
@@ -99,7 +101,7 @@
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
 /* start of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
+#define	CFG_GBL_DATA_OFFSET	(CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
 
 /* monitor code */
 #define	SIZE			0x40000
@@ -145,6 +147,16 @@
 	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 #endif /* !FLASH */
 
+/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
+	#define	CONFIG_SYSTEMACE
+	/* #define DEBUG_SYSTEMACE */
+	#define	SYSTEMACE_CONFIG_FPGA
+	#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+	#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+	#define	CONFIG_DOS_PARTITION
+#endif
+
 /*
  * BOOTP options
  */
@@ -153,28 +165,21 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_AUTOSCRIPT
-#define CONFIG_CMD_BDI
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMI
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
 #define CONFIG_CMD_MFSL
-#define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
+
+#if defined(CONFIG_SYSTEMACE)
+	#define CONFIG_CMD_EXT2
+	#define CONFIG_CMD_FAT
+#endif
 
 #if defined(FLASH)
 	#define CONFIG_CMD_ECHO
@@ -186,6 +191,8 @@
 		#define CONFIG_CMD_ENV
 		#define CONFIG_CMD_SAVES
 	#endif
+#else
+	#undef CONFIG_CMD_FLASH
 #endif
 
 #if defined(CONFIG_CMD_JFFS2)
@@ -210,24 +217,16 @@
 #define	CONFIG_BOOTDELAY	30
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		"ml401"
-#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
+#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
 #define	CONFIG_IPADDR		192.168.0.3
-#define	CONFIG_SERVERIP 	192.168.0.5
-#define	CONFIG_GATEWAYIP 	192.168.0.1
+#define	CONFIG_SERVERIP		192.168.0.5
+#define	CONFIG_GATEWAYIP	192.168.0.1
 #define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
 
 /* architecture dependent code */
 #define	CFG_USR_EXCEP	/* user exception */
 #define CFG_HZ	1000
 
-/* system ace */
-#define	CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-#define	SYSTEMACE_CONFIG_FPGA
-#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define	CONFIG_DOS_PARTITION
-
 #define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"
 
 #define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\

include/configs/stxssa.h

@@ -189,20 +189,21 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
+/*
+ * I2C
+ */
 #define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#if 0
-#define CFG_I2C_NOPROBES	{0x00}	/* Don't probe these addrs */
-#else
-/* I did the 'if 0' so we could keep the syntax above if ever needed. */
 #undef CFG_I2C_NOPROBES
-#endif
 #define CFG_I2C_OFFSET		0x3000
 
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* This is really a DS1339 RTC	*/
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
 /* I2C EEPROM.	AT24C32, we keep our environment in here.
 */
 #define CFG_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
@@ -341,8 +342,13 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/suzaku.h

@@ -48,6 +48,7 @@
 #define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 #define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - (1024 * 1024))
 
+#define CONFIG_XILINX_UARTLITE
 #define CONFIG_BAUDRATE		115200
 #define CFG_BAUDRATE_TABLE	{ 115200 }
 
@@ -55,21 +56,16 @@
 #define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
 #define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_MISC
 
 #define CFG_UART1_BASE		(0xFFFF2000)
 #define CONFIG_SERIAL_BASE	CFG_UART1_BASE
@@ -108,4 +104,7 @@
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
+#define XILINX_CLOCK_FREQ	50000000
+#define CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
+
 #endif	/* __CONFIG_H */

include/configs/xupv2p.h

 /*
- * (C) Copyright 2007 Czech Technical University.
+ * (C) Copyright 2007 Michal Simek
  *
  * Michal SIMEK <monstr@monstr.eu>
  *
@@ -31,6 +31,7 @@
 #define	CONFIG_XUPV2P		1
 
 /* uart */
+#define CONFIG_XILINX_UARTLITE
 #define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
 #define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

include/led.h

-/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __LED_H
-#define __LED_H
-
-#ifndef	__ASSEMBLY__
-extern void	LED_init (void);
-extern void	red_LED_on(void);
-extern void	red_LED_off(void);
-extern void	green_LED_on(void);
-extern void	green_LED_off(void);
-extern void	yellow_LED_on(void);
-extern void	yellow_LED_off(void);
-#else
-	.extern LED_init
-	.extern red_LED_on
-	.extern red_LED_off
-	.extern yellow_LED_on
-	.extern yellow_LED_off
-	.extern green_LED_on
-	.extern green_LED_off
-#endif
-#endif

include/linux/mtd/bbm.h

+/*
+ *  linux/include/linux/mtd/bbm.h
+ *
+ *  NAND family Bad Block Management (BBM) header file
+ *    - Bad Block Table (BBT) implementation
+ *
+ *  Copyright (c) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Copyright (c) 2000-2005
+ *  Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef NAND_MAX_CHIPS
+#define NAND_MAX_CHIPS		8
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options	options for this descriptor
+ * @param pages		the page(s) where we find the bbt, used with
+ * 			option BBT_ABSPAGE when bbt is searched,
+ * 			then we store the found bbts pages here.
+ *			Its an array and supports up to 8 chips now
+ * @param offs		offset of the pattern in the oob area of the page
+ * @param veroffs	offset of the bbt version counter in the oob are of the page
+ * @param version	version read from the bbt page during scan
+ * @param len		length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks	maximum number of blocks to search for a bbt. This number of
+ *			blocks is reserved at the end of the device
+ *			where the tables are written.
+ * @param reserved_block_code	if non-0, this pattern denotes a reserved
+ *			(rather than bad) block in the stored bbt
+ * @param pattern	pattern to identify bad block table or factory marked
+ *			good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int options;
+	int pages[NAND_MAX_CHIPS];
+	int offs;
+	int veroffs;
+	uint8_t version[NAND_MAX_CHIPS];
+	int len;
+	int maxblocks;
+	int reserved_block_code;
+	uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH		0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE		0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS	0
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift	[INTERN] number of address bits in a bbt entry
+ * @param badblockpos		[INTERN] position of the bad block marker in the oob area
+ * @param bbt			[INTERN] bad block table pointer
+ * @param badblock_pattern	[REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv			[OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+	int bbt_erase_shift;
+	int badblockpos;
+	int options;
+
+	uint8_t *bbt;
+
+	int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+
+	/* TODO Add more NAND specific fileds */
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt (struct mtd_info *mtd);
+
+#endif				/* __LINUX_MTD_BBM_H */

include/linux/mtd/onenand.h

+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/mtd/onenand_regs.h>
+
+/* Note: The header order is impoertant */
+#include <onenand_uboot.h>
+
+#include <linux/mtd/bbm.h>
+
+#define MAX_BUFFERRAM		2
+#define MAX_ONENAND_PAGESIZE	(2048 + 64)
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release (struct mtd_info *mtd);
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block		block address in BufferRAM
+ * @param page		page address in BufferRAM
+ * @param valid		valid flag
+ */
+struct onenand_bufferram {
+	int block;
+	int page;
+	int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param readw		[REPLACEABLE] hardware specific function for read short
+ * @param writew	[REPLACEABLE] hardware specific function for write short
+ * @param command	[REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem *base;
+	unsigned int chipsize;
+	unsigned int device_id;
+	unsigned int options;
+
+	unsigned int erase_shift;
+	unsigned int page_shift;
+	unsigned int ppb_shift;	/* Pages per block shift */
+	unsigned int page_mask;
+
+	unsigned int bufferram_index;
+	struct onenand_bufferram bufferram[MAX_BUFFERRAM];
+
+	int (*command) (struct mtd_info * mtd, int cmd, loff_t address,
+			size_t len);
+	int (*wait) (struct mtd_info * mtd, int state);
+	int (*read_bufferram) (struct mtd_info * mtd, int area,
+			       unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram) (struct mtd_info * mtd, int area,
+				const unsigned char *buffer, int offset,
+				size_t count);
+	unsigned short (*read_word) (void __iomem * addr);
+	void (*write_word) (unsigned short value, void __iomem * addr);
+	void (*mmcontrol) (struct mtd_info * mtd, int sync_read);
+
+	spinlock_t chip_lock;
+	wait_queue_head_t wq;
+	onenand_state_t state;
+
+	struct nand_oobinfo *autooob;
+
+	void *bbm;
+
+	void *priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK		(0x0001)
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG	0xec
+#define ONENAND_MFR_UNKNOWN	0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+	int id;
+	char *name;
+};
+
+#endif				/* __LINUX_MTD_ONENAND_H */

include/linux/mtd/onenand_regs.h

+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
+#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
+#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
+#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
+#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+#endif				/* __ONENAND_REG_H */

include/onenand_uboot.h

+/*
+ *  Header file for OneNAND support for U-Boot
+ *
+ *  Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_ONENAND_H
+#define __UBOOT_ONENAND_H
+
+struct kvec {
+	void *iov_base;
+	size_t iov_len;
+};
+
+typedef int spinlock_t;
+typedef int wait_queue_head_t;
+
+/* Functions */
+extern void onenand_init(void);
+extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t * retlen, u_char * buf);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+			    size_t * retlen, u_char * buf);
+extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
+			 size_t * retlen, const u_char * buf);
+extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
+
+extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
+
+extern void onenand_print_device_info(int device, int verbose);
+
+#endif /* __UBOOT_ONENAND_H */

include/status_led.h

@@ -383,6 +383,27 @@ extern void __led_set (led_id_t mask, int state);
 # include <asm/status_led.h>
 #endif
 
+/*
+ * Coloured LEDs API
+ */
+#ifndef	__ASSEMBLY__
+extern void	coloured_LED_init (void);
+extern void	red_LED_on(void);
+extern void	red_LED_off(void);
+extern void	green_LED_on(void);
+extern void	green_LED_off(void);
+extern void	yellow_LED_on(void);
+extern void	yellow_LED_off(void);
+#else
+	.extern LED_init
+	.extern red_LED_on
+	.extern red_LED_off
+	.extern yellow_LED_on
+	.extern yellow_LED_off
+	.extern green_LED_on
+	.extern green_LED_off
+#endif
+
 #endif	/* CONFIG_STATUS_LED	*/
 
 #endif	/* _STATUS_LED_H_	*/

lib_arm/board.c

@@ -58,6 +58,10 @@ DECLARE_GLOBAL_DATA_PTR;
 void nand_init (void);
 #endif
 
+#if defined(CONFIG_CMD_ONENAND)
+void onenand_init(void);
+#endif
+
 ulong monitor_flash_len;
 
 #ifdef CONFIG_HAS_DATAFLASH
@@ -111,6 +115,26 @@ void *sbrk (ptrdiff_t increment)
 	return ((void *) old);
 }
 
+/************************************************************************
+ * Coloured LED functionality
+ ************************************************************************
+ * May be supplied by boards if desired
+ */
+void inline __coloured_LED_init (void) {}
+void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
+void inline __red_LED_on (void) {}
+void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
+void inline __red_LED_off(void) {}
+void inline red_LED_off(void)	     __attribute__((weak, alias("__red_LED_off")));
+void inline __green_LED_on(void) {}
+void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
+void inline __green_LED_off(void) {}
+void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off")));
+void inline __yellow_LED_on(void) {}
+void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
+void inline __yellow_LED_off(void) {}
+void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
+
 /************************************************************************
  * Init Utilities							*
  ************************************************************************
@@ -185,7 +209,6 @@ static void display_flash_config (ulong size)
 }
 #endif /* CFG_NO_FLASH */
 
-
 /*
  * Breathe some life into the board...
  *
@@ -301,6 +324,10 @@ void start_armboot (void)
 	nand_init();		/* go init the NAND */
 #endif
 
+#if defined(CONFIG_CMD_ONENAND)
+	onenand_init();
+#endif
+
 #ifdef CONFIG_HAS_DATAFLASH
 	AT91F_DataflashInit();
 	dataflash_print_info();

lib_avr32/board.c

@@ -310,10 +310,20 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 	malloc_bin_reloc();
 	dma_alloc_init();
 	board_init_info();
-	flash_init();
+
+	bd->bi_flashstart = 0;
+	bd->bi_flashsize = 0;
+	bd->bi_flashoffset = 0;
+
+#ifndef CFG_NO_FLASH
+	bd->bi_flashstart = CFG_FLASH_BASE;
+	bd->bi_flashsize = flash_init();
+	bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
 
 	if (bd->bi_flashsize)
 		display_flash_config();
+#endif
+
 	if (bd->bi_dram[0].size)
 		display_dram_config();
 

lib_microblaze/time.c

@@ -26,9 +26,17 @@
 
 #include <common.h>
 
+#ifdef CFG_TIMER_0
 void udelay (unsigned long usec)
 {
 	int i;
 	i = get_timer (0);
 	while ((get_timer (0) - i) < (usec / 1000)) ;
 }
+#else
+void udelay (unsigned long usec)
+{
+	unsigned int i;
+	for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++);
+}
+#endif