Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.

The Aries Embedded boards have been removed with commit 03b54997
("board/aries: Remove"). I will now take care of them.

The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".
Signed-off-by: NWolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The stratix 10 reset manager ad-hoc code in arch/arm contains an unused
function 'reset_deassert_peripherals_handoff' that has been added from
the beginning. As this is probably a result of copying the gen5 reset
manager and this function has never been used, remove it.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

commit c5de2b7e ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.

While at it, remove this function for gen5 as it should not be used.

Fixes: commit c1d4b464 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Pull request for UEFI sub-system for v2019.07-rc3

The development target for the UEFI sub-system is EBBR compliance. We have
already implemented some further protocols to enable running the UEFI Shell
and the UEFI SCT test suite.

As some boards are severely memory constrained make some of these extras
customizable.

Provide bug fixes. The most prominent ones let us pass the UEFI SCT memory
allocation tests.

- A10 FPGA programming support, Gen5 livetree conversion

- SH2, SH3 removal

Describe that efi_install_fdt() defaults to using the device tree
indicated by environment variable fdtcontroladdr.

ACPI tables and device trees are mutually exclusive.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Move duplicate initialization code to single instance.

Adjust comments of concerned functions.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The device path to text protocol renders ACPI device nodes incorrectly.

Use capital hexadecimal numbers as shown in the UEFI spec examples.

Always output the optional UID. This matches what UEFI SCT expects and
saves us an `if`.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

UEFI SCT uses this call sequence to determine the current TPL level inside
notification functions:

    OldTpl = BS->RaiseTPL(TPL_HIGH_LEVEL);
    BS->RestoreTPL(OldTpl);

In RestoreTPL() we trigger the notification function of queued events. If
we do not mark the event as non-queued before calling the notification
function, this results in an infinite recursive call sequence.

Mark the event as non-queued before entering the notification function.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Replace unnecessary control structures by using return statements.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

If AllocatePages() is called with AllocateAddress, the UEFI spec requires
to return EFI_NOT_FOUND in case the memory page does not exist.

The UEFI SCT II 2017 spec additionally requires to return EFI_NOT_FOUND if
the page is already allocated.

Check that *Memory refers to an unallocated page.

UEFI SCT II (2017): AllocatePages(), 5.1.2.1.9 - 5.1.2.1.10
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

According to the UEFI AllocatePages() has to return EFI_OUT_OF_RESOURCES if
sufficient memory is not available.

Change the return value.

UEFI SCT II (2017): 3.2.1 AllocatePages(), 5.1.2.1.8
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

When we call FreePages() we essentially add memory to our memory map. We
shouldn't do this for memory that does not exit.

Check if the memory that is to be freed via FreePages() or FreePool() is in
our memory map and is not EFI_CONVENTIONAL_MEMORY.

This check is mandated by the UEFI specification.

Cf. UEFI SCT  II (2017), 3.2.2 FreePages(), 5.1.2.1 - 5.1.2.2
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

According to the UEFI specification UninstallProtocolInteface() has to
return EFI_NOT_FOUND if the interface is not found.

Correct the return value.

Cf. UEFI SCT II spec (2017), 3.3.2 UninstallProtocolInterface(), 5.1.3.2.4
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

efi_search_protocol() already checks that the GUID matches. Don't check
a second time.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

A parameter check in LocateDevicePath() does not match the requirements of
the UEFI spec.

If device is NULL, only return EFI_INVALID_PARAMETER if a matching handle
is found.

Cf. UEFI SCT II specification (2017)3.3.7 LocateDevicePath(), 5.1.3.7.3
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

%s/not buffer/no buffer/
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The device path to text protocol is not needed for EBBR compliance. So
let's make it a customizable option.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The Unicode collation protocol is not needed for EBBR compliance. So let's
make it a customizable option.

The Unicode capitalization table is only needed by this protocol. So let it
depend on the Unicode collation protocol.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

No need to mention U-Boot in brief description.
Fix several typos, mention iPXE.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Use if/endif for dependencies to give structure to the configuration menu.

Sort important settings to the top.

Abbreviate the short description of EFI_LOADER_HII.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

If EFI_LOADER_HII is not set, do not unnecessarily compile files for HII
protocols.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Assign include/charset.h to EFI PAYLOAD.

The functions defined in this include are used by the UEFI sub-system.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Correct the description of utf8_utf16_strnlen() and utf8_utf16_strlen() to
reflect that they return u16 count and not byte count.

For these functions and utf16_utf8_strnlen() describe the handling of
invalid code sequences.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'socfpga_reset_probe' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int'.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to
read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to
read flash (child node) parameters.

Tested on socfpga_socrates (socfpga gen5).
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The dw-apb timer does not use 'gd', so remove its declaration.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Fix SPI flash environment erase size error.

CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
to allow erase one environment sector.

Fix error below:

SOCFPGA_STRATIX10 # saveenv
Saving Environment to SPI Flash...
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Erasing SPI flash...SF: Erase offset/length not multiple of erase size
Failed (-22)
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
. The result of calculation is come from default max cluster(0x10000) +
others(0x2000) + additional memory for headroom(0x3000).
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Update the default configuration file to enable the necessary functionality
the get the kit working.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Update the default configuration file to enable the necessary functionality
to get the SoCFPGA loadfs driver support. This would enable the
implementation of programming bitstream into FPGA from MMC.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>