The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: NTom Rini <trini@konsulko.com>

Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.

The G (gesture) key remains unused at this point.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.

A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.

Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

This adds support for resetting the device on a long press on the power button.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>
[trini: Update to use Kconfig for MUSB]
Signed-off-by: NTom Rini <trini@konsulko.com>

Now that the serial number is correctly defined, we can pass it to the kernel
using the (legacy) ATAG method. It will be automatically passed via device-tree
when enabled.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

The OMAP3 has some die-specific ID bits that we can use to give the device a
(more or less) unique serial number. This is particularly useful for e.g. USB.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>

This adds support for the omap3 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.

It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.

For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-partSigned-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: NTom Rini <trini@konsulko.com>

Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.

This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.

It is up to each board to make use of this mechanism or not.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

This allows scanning the twl4030 keypad, storing the result in a 64-byte long
matrix with the twl4030_keypad_scan function.

Detecting a key at a given column and row is made easier with the
twl4030_keypad_key function.
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>
Reviewed-by: NTom Rini <trini@konsulko.com>

This adds support for detecting a few inputs exported by the TWL4030.
Currently-supported inputs are the power button, USB and charger presence.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>

This adds support for powering off (the omap3 SoC) from the twl4030. This is
especially useful when the kernel does not actually power off the device using
this method but reboots and leaves it up to the bootloader to actually turn the
power off.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: NPaul Kocialkowski <contact@paulk.fr>

The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.

Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Tested-by: NSylvain Lemieux <slemieux@tycoint.com>

Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: NScott Wood <scottwood@freescale.com>

If a dtb is specified on the command-line, the Android boot image ramdisk
will not be found. Fix this so that we can specify the ramdisk address and
dtb address. The syntax is to enter the Android boot image address for
both the kernel and ramdisk.
Signed-off-by: NRob Herring <robh@kernel.org>

When building the file system the existing code does an insertion into
a linked list. It attempts to speed this up by keeping a pointer to
where the last entry was inserted but it's still slow.

Now the nodes are just inserted into the list without searching
through for the correct place. This unsorted list is then sorted once
using mergesort after all the entries have been added to the list.
This speeds up the scanning of the flash file system considerably.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

If a sector has a CLEANMARKER at the beginning, it indicates that the
entire sector has been erased. Therefore, if this is found, we can skip the
entire block. This was not being done before this patch.

The code now does the same as the kernel does when encountering a
CLEANMARKER. It still checks that the next few words are FFFFFFFF, and if
so, the block is assumed to be empty, and so is skipped.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

The scan code is similar to the linux kernel, but the kernel defines a much
smaller size to scan through before deciding a sector is blank. Assuming
that what is in the kernel is OK, make these two match.

On its own, this change makes no difference to scanning of any sectors
which have a clean marker at the beginning, since the entire sector is not
blank.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

If the flash is slow, reading less from the flash into buffers makes
the process faster.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

jffs2_1pass_read_inode() would read the entire data for each node
in the filesystem, regardless of whether it was part of the file
to be loaded or not. By only reading the header data for an inode,
and then reading the data only when it is found to be part of the
file to be loaded, much copying of data is saved.

jffs2_1pass_list_inodes() read each inode for every file in the
directory into a buffer. By using NULL as a buffer pointer, NOR
flash simply returns a pointer, and therefore avoids a memory copy.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

If multiple versions of a file exist, only the most recent version
should be used. The scheme to write 0 for the inode in older versions
did not work, since this would have required writing to flash.

The only time this caused an issue was listing a directory, where older
versions of the file would still be seen. Since the directory entries
are sorted, just look at the next entry in the list, and if it's the same
move to that entry instead.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

Copying complete nodes from flash can be slow if the flash is slow
to read. By only reading the data needed, the sorting operation can
be made much faster.

The directory entry comparison function also had a two bugs. First, it
did not ensure the name was copied, so the name comparison may have
been faulty (although it would have worked with NOR flash).  Second,
setting the ino to zero to ignore the entry did not work, since this
was either writing to a temporary buffer, or (for NOR flash) directly
to flash. Either way, the change was not remembered.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

If a destination is not provided, jffs2_1pass_read_inode() only
returns the length of the file. In this case, avoid reading all
the data nodes, and return as soon as the length of the file is
known.
Signed-off-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>

Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC
Signed-off-by: NJiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: NSteve Rae <srae@broadcom.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:

RomBOOT
>

U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)

CPU: AT91SAM9260
Crystal frequency:   18.432 MHz
CPU clock        :  198.656 MHz
Master clock     :   99.328 MHz
       Watchdog enabled
DRAM:  64 MiB
WARNING: Caches not enabled
NAND:  256 MiB
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Hit any key to stop autoboot:  0
U-Boot>
Signed-off-by: NHeiko Schocher <hs@denx.de>

remove unneeded udelay() in this function, as we use
the dev_ready pin.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Acked-by: NScott Wood <scottwood@freescale.com>

This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.
Signed-off-by: NHeiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: NTom Rini <trini@konsulko.com>

remove options defined in the distro defaults
add distro bot commands
set scriptaddr value
Signed-off-by: NDennis Gilmore <dennis@ausil.us>

Signed-off-by: NDennis Gilmore <dennis@ausil.us>

PXE: if a board has set its own value for CONFIG_BOOTP_VCI_STRING do not set the default one. Use the board set value instead
Signed-off-by: NDennis Gilmore <dennis@ausil.us>

On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in the DT are already
correct, so remove U-Boot's DRAM bank setup so the memory node is not
"fixed up" by u-boot.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndre Przywara <osp@andrep.de>

These were pointed out in review but I missed them.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The return type of pmic_read and pmic_write is signed int, so
correct variable 'ret' from type unsigned int to int.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>

If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>