ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: NAlexander Stein <alexanders83@web.de> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Tested-by: NStephen Warren <swarren@wwwdotorg.org>
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