- Relocate the location of U-Boot in the flash
- Save the environment in one sector of the flash memory
- MTD Support
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch allows booting from FLASH the ML507 board by Xilinx.
Previously, U-Boot needed to be loaded from JTAG or a Sytem ACE CF
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>

The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
	among others:
	-Virtex 5 FX FPGA (With a ppc440x5 in it)
	-256MB of SDRAM2
	-32MB of Flash
	-I2C Eeprom
	-System ACE chip
	-Serial ATA connectors
	-RS232 Level Conversors
	-Ethernet Transceiver

This patch gives support to a standard design produced by EDK for this
board: ppc440, uartlite, xilinx_int and flash

- Includes Changes propossed by Stefan Roese and Michal Simek
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: NStefan Roese <sr@denx.de>

The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats.  The
NXID format replaces the older CCID format, but it's important to support both
since most boards out there still use the CCID format.  This change is in
preparation for using one file to handle both formats.  This will also unify
EEPROM support for all Freescale 85xx and 86xx boards.

Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR
instead of ID_EEPROM_ADDR.
Signed-off-by: NTimur Tabi <timur@freescale.com>

The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out.  In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board.  As that constitutes the vast majority of
users, we remove it.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Make the default build for the sbc8560 board be powerpc
capable with libfdt support.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

This was proposed by Paul Gortmaker in response to Wolfgang's comments on
similar #defines in sbc8560.h.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add in the default fdt settings and the typical EXTRA_ENV
settings as borrowed from the mpc8560ads.  Fix a couple
of stale references to the mpc8560ads dating back to the
original clone/fork.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The existing config doesn't define CONFIG_HAS_ETH0, and so the
fdt support doesn't update the zeros in the dtb local-mac with
real data from the u-boot env.  Since the existing config is
tailored to just two interfaces, get rid of the ETH2 definitions
at the same time.

Also don't include any end user specific data into the environment
by default -- things like MAC address, network parameters etc. need
to come from the end user.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The definitions for the TSEC have become out of date.  There is no
longer any such options like "CONFIG_MPC85xx_TSEC1" or similar.
Update to match those of other boards, like the MPC8560ADS.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NBen Warren <biggerbadderben@gmail.com>

The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NStefan Roese <sr@denx.de>

caused by missing dcache status/enable/disable functions.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>

Add #define CONFIG_MCFTMR in EB+MCF-EV123.h configuration file
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NKurt Mahan <kmahan@freescale.com>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.
Signed-off-by: NStefan Roese <sr@denx.de>

This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NFeng Kan <fkan@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

ADS5121 Rev 3 board is now the default config

config targets are now

ads5121_config
    Rev 3 board with
	PCI
	M41T62 on board RTC
	512MB DRAM

ads5121_rev2_config
    Rev 2 board with
	No PCI
	256MB DRAM
Signed-off-by: NMartha Marx <mmarx@silicontkx.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJohn Rigby <jrigby@freescale.com>

Consolidate ADS5121 IO Pin configuration to one file
board/ads5121/iopin.c.

Remove pin config from cpu/mpc512x/fec.c
Signed-off-by: NMartha Marx <mmarx@silicontkx.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJohn Rigby <jrigby@freescale.com>

Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.

Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NLarry Johnson <lrj@acm.org>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NLarry Johnson <lrj@acm.org>
Signed-off-by: NStefan Roese <sr@denx.de>

ARM: Fix for incorrect version of patch applied when
adding support for the Lyrtech SFF-SDR board.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>
Signed-off-by: NPhilip Balister, OpenSDR <philip@opensdr.com>

After we move the atmel_mci driver into drivers/mmc, we can't select
it with CONFIG_MMC anymore. Introduce a new symbol specifically for
this driver so that there's no ambiguity.
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
Acked-by: NJean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NMatvejchikov Ilya <matvejchikov@gmail.com>

Disable SH ether driver.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The watchdog on 8610 board is enabled by setting sw[6]
to on. Once enabled, the watchdog can not be disabled
by software. So feed the dog in u-boot is necessary for
normal operation.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>

New NOR Flash board support and remove old type flash board config.
And Remove network setting from config file.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

New NOR Flash board support and remove network setting from config file.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Remove network setting from config file.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Remove network setting from config file.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>