- Relocate the location of U-Boot in the flash
- Save the environment in one sector of the flash memory
- MTD Support
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch allows booting from FLASH the ML507 board by Xilinx.
Previously, U-Boot needed to be loaded from JTAG or a Sytem ACE CF
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
	among others:
	-Virtex 5 FX FPGA (With a ppc440x5 in it)
	-256MB of SDRAM2
	-32MB of Flash
	-I2C Eeprom
	-System ACE chip
	-Serial ATA connectors
	-RS232 Level Conversors
	-Ethernet Transceiver

This patch gives support to a standard design produced by EDK for this
board: ppc440, uartlite, xilinx_int and flash

- Includes Changes propossed by Stefan Roese and Michal Simek
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: NStefan Roese <sr@denx.de>

-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: NStefan Roese <sr@denx.de>

The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats.  The
NXID format replaces the older CCID format, but it's important to support both
since most boards out there still use the CCID format.  This change is in
preparation for using one file to handle both formats.  This will also unify
EEPROM support for all Freescale 85xx and 86xx boards.

Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR
instead of ID_EEPROM_ADDR.
Signed-off-by: NTimur Tabi <timur@freescale.com>

The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out.  In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board.  As that constitutes the vast majority of
users, we remove it.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add new L1/L2 SPRs related to e500mc cache config and control.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Make the default build for the sbc8560 board be powerpc
capable with libfdt support.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

This was proposed by Paul Gortmaker in response to Wolfgang's comments on
similar #defines in sbc8560.h.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add in the default fdt settings and the typical EXTRA_ENV
settings as borrowed from the mpc8560ads.  Fix a couple
of stale references to the mpc8560ads dating back to the
original clone/fork.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The existing config doesn't define CONFIG_HAS_ETH0, and so the
fdt support doesn't update the zeros in the dtb local-mac with
real data from the u-boot env.  Since the existing config is
tailored to just two interfaces, get rid of the ETH2 definitions
at the same time.

Also don't include any end user specific data into the environment
by default -- things like MAC address, network parameters etc. need
to come from the end user.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The definitions for the TSEC have become out of date.  There is no
longer any such options like "CONFIG_MPC85xx_TSEC1" or similar.
Update to match those of other boards, like the MPC8560ADS.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NBen Warren <biggerbadderben@gmail.com>

Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NStefan Roese <sr@denx.de>

Clean Makefile
Move device specific values to driver for better reading
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NStefan Roese <sr@denx.de>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

Redesign uartlite driver to in_be32 and out_be32 macros
Fix missing header in io.h
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

caused by missing dcache status/enable/disable functions.
Signed-off-by: NHugo Villeneuve <hugo.villeneuve@lyrtech.com>

Add #define CONFIG_MCFTMR in EB+MCF-EV123.h configuration file
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

The timer was assigned to wrong timer memory mapped which
caused udelay() and timer() not working properly.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NKurt Mahan <kmahan@freescale.com>

Signed-off-by: NStefan Roese <sr@denx.de>

Only the really needed ones are added (cascading and EMAC/MAL).
Signed-off-by: NStefan Roese <sr@denx.de>

This patch continues the ppc440.h cleanup by removing some of the unused
defines.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.

Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: NStefan Roese <sr@denx.de>

This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add additional DDR2 SDRAM memory controller DCR mneomnics, condition
revision ID DCR based on 405EX, and add field mnemonics for bus error
status and ECC error status registers.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds bit field mnemonics for the 405EX(r) SDR0_SRST soft reset register.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Signed-off-by: NStefan Roese <sr@denx.de>