Commit be3b51aa did this mostly, but several have been added since. Do the
job again.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This is not used by any boards now. Drop it to avoid confusion.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Now that the GPIO numbering series has been applied, we can use the correct
GPIO for the EC interrupt.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

It's removed the exynos5_gpio_part1.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Set the ddr mode capability by default.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Enabled the dw-mmc controller.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Support the DDR mode at dw-mmc controller
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NLukasz Majeski <l.majewski@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Restore the platdata(property of dt) into host struct.
Then data's information is maintained and reused anywhere.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Exynos4 can be used the dwmmc controller for eMMC.
Then it needs to check dwmmc_init() at first.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NPiotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

exynos4x12_set_mmc_clk function have been removed.
Because, exynos4x12_clock and exynos4_clock return same div_fsys* value.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NPiotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

For use dwmmc controller at exynos4, add SDMMC4 gpio configuration.
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Tested-by: NPiotr Wilczek <p.wilczek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

UMS-related defines were added to Samsung Goni config header.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Proper adjustment for supporting DFU at GONI target has been made.
The s5p_goni.h file has been updated. Moreover the code for low level
USB initialization has been added to GONI board code.

The malloc pool has been enlarged in order to support larger buffer
sizes needed by DFU implementation.
Signed-off-by: NArkadiusz Wlodarczyk <a.wlodarczyk@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Tested-by: NArkadiusz Wlodarczyk <a.wlodarczyk@samsung.com>
Tested-by: NMateusz Zalega <m.zalega@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Configuration file for GONI has been updated to support FAT file system,
new mmc partitioning scheme and read linux kernel from eMMC instead of
OneNAND.
Signed-off-by: NArkadiusz Wlodarczyk <a.wlodarczyk@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Tested-by: NArkadiusz Wlodarczyk <a.wlodarczyk@samsung.com>
Tested-by: NMateusz Zalega <m.zalega@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: NMarek Vasut <marex@denx.de>

CPUs arm946es and sa1100 both define the reset_cpu()
function in their start.S file. Move this cpu-specific code
into cpu.c so that start.S only contains ARM generic code.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.

Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:

repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]

According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.

At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.

An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.

While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.

Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The Venice2 pinmux spreadsheet was updated to fix a few issues. Import
those changes into the U-Boot pinmux initialization tables.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This re-imports the entire Venice2 pinmux data from the board's master
spreadsheet, and makes use of the new IO clamping GPIO initialization
table features. This makes the board port fully compliant with the
required HW-defined pinmux initialization sequence.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Modify the Jetson TK1 board to do this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. This patch implements this
procedure for Jetson TK1. For pins which are to be used as GPIOs, the
pinmux mux function need not be programmed, so the pinmux table is also
adjusted.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.

For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE

1) It isn't documented in README. The same is true for a lot of similar
   defines used by api_storage.c.

2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
   valid values are 0..n-1 not 0..n.

However, I this patch does not address those shortcomings.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Enabling configs for GPIO CMD, EXYNOS4 family and replacing
exynos_gpio_get with new linear GPIO pin number required
because of the new function asking only 2 arguments (pin
and value) instead of 3 (bank, pin and value).
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>