ARM: tegra: update Venice2 pinmux

This re-imports the entire Venice2 pinmux data from the board's master
spreadsheet, and makes use of the new IO clamping GPIO initialization
table features. This makes the board port fully compliant with the
required HW-defined pinmux initialization sequence.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

board/nvidia/venice2/venice2.c

@@ -6,12 +6,9 @@
  */
 
 #include <common.h>
-#include <asm-generic/gpio.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
 #include "pinmux-config-venice2.h"
-#include <i2c.h>
 
 /*
  * Routine: pinmux_init
@@ -19,16 +16,14 @@
  */
 void pinmux_init(void)
 {
-	pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
-		ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+	pinmux_set_tristate_input_clamping();
 
-	pinmux_config_pingrp_table(tegra124_pinmux_common,
-		ARRAY_SIZE(tegra124_pinmux_common));
+	gpio_config_table(venice2_gpio_inits,
+			  ARRAY_SIZE(venice2_gpio_inits));
 
-	pinmux_config_pingrp_table(unused_pins_lowpower,
-		ARRAY_SIZE(unused_pins_lowpower));
+	pinmux_config_pingrp_table(venice2_pingrps,
+				   ARRAY_SIZE(venice2_pingrps));
 
-	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
-	pinmux_config_drvgrp_table(venice2_padctrl,
-		ARRAY_SIZE(venice2_padctrl));
+	pinmux_config_drvgrp_table(venice2_drvgrps,
+				   ARRAY_SIZE(venice2_drvgrps));
 }