- 31 7月, 2016 7 次提交
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由 jk.kernel@gmail.com 提交于
Add an extra byte so that this data is not byteswapped. Signed-off-by: NZiyuan Xu <jk.kernel@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
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由 John Keeping 提交于
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
Update MAINTAINER files for kylin_rk3036, evb_rk3036. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Angelo Dureghello 提交于
This patch is style-related only, to reformat all the start.S code, actually not following a coherent style inside single files and between different cpu start.S files. Linux format has been respected, as - max line width at 80 columns - one 8 cols tab between asm instructions and operands - inline comments, where any, fixed at col 41 Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
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- 30 7月, 2016 12 次提交
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由 Vignesh R 提交于
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the board connected to TI QSPI IP over CS0. Therefore enable QSPI support. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable CONFIG_SPI_FLASH_BAR to access flash regions above 16MB. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
Now that QSPI driver can support 76.8MHz, update the CONFIG_SF_DEFAULT_SPEED to the same value. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Lokesh Vutla 提交于
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Wenyou Yang 提交于
Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
As per commit b545a98f ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Moritz Fischer 提交于
This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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- 28 7月, 2016 21 次提交
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由 Fabio Estevam 提交于
Pass the board/freescale/*mx*/ path as files maintained by Stefano Babic. While this is not ideal and does not cover all the i.MX board cases, it gives at least a better hint for the /scripts/get_maintainer.pl tool. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
Add an entry for the mx7dsabresd_secure_defconfig target. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Stefan Agner 提交于
Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize the generic timer on all CPU's. This allows to make use of the timer freuquency register also on other CPU than the start CPU which is important for KVM. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Diego Dorta 提交于
Remove unused define constant. Signed-off-by: NDiego Dorta <diego.dorta@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
novena uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Marek Vasut <marex@denx.de> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Martin Donnelly <martin.donnelly@ge.com> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
Currently it's recommended to move some configuration options to the defconfig file. Move some USB related options to the defconfig file. Signed-off-by: NBreno Lima <breno.lima@nxp.com>
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由 Stefan Agner 提交于
This commit adds support for the Toradex Computer on Modules Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence can be easily supported by one board. The board code detects RAM size at runtime which is one of the differences between the two boards. The board also uses the UART's in DTE mode, hence making use of the new DTE support via serial DM. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Breno Lima 提交于
It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
It's not necessary to use the is_cpu_type function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Tim Harvey 提交于
Added removal of the fsl,ext-reset-output property in the wdog node for board revisions that pre-date the addition of the external watchdog reset signal. This property is a recent addition to mainline linux kernel in order to specify that the IMX watchdog external reset should be used instead of the internal chip-level reset. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Re-factor the board-specific dt fixups so that they are easier to follow and extend in the future: - use defines for DT paths - use switch/case per board - order models numerically There is no functional change in the code Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The hwconfig env var allows user to control hardware specific configuration of board specific features but not all Ventana boards have the same features. We will use the magic default value of "_UNKNOWN_" to signify that the bootloader should create this based on detected board model. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana product family. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Replace the static list of board-specific digital I/O's with a dynamic list. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Not all Ventana boards have an RS232 transceiver, make it board specific. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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