- 01 9月, 2012 40 次提交
-
-
由 Laurence Withers 提交于
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: NLaurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Remove Sandeep, thanks for all the hard work! Signed-off-by: NTom Rini <trini@ti.com>
-
由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NTom Rini <trini@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
-
由 Marek Vasut 提交于
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NTom Rini <trini@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
am33xx boards have at least one eeprom and in the case of beaglebones with capes, more. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
- Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
The intention has always been (and boards are to support) an i2c EEPROM that will identify what hardware they are, allowing a single binary to support multiple boards. As such, remove the 'evm.c' file as there is nothing EVM centric in it currently, only SoC peripheral configuration. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Vaibhav Bedia 提交于
EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335xSigned-off-by: NVaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
- Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
With the previous bugfix we now don't need to set two different REF_CTRL values and instead set the final value. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
When we change SDRAM_CONFIG this triggers a refresh based on all of the parameters that we have programmed so we must do this last. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
The am33xx does not have a DMM, so don't define the base. Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
- Add default commands - Add HUSH parser - Make environment, malloc areas larger - Add ATAGS and OF_LIBFDT - Add defaults to boot ramdisk and MMC, use uEnv.txt Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
-
由 Javier Martinez Canillas 提交于
This patch adds SPL support for IGEP-based boards. Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory. Signed-off-by: NJavier Martinez Canillas <javier@dowhile0.org>
-
由 Javier Martinez Canillas 提交于
Signed-off-by: NJavier Martinez Canillas <javier@dowhile0.org>
-
由 Javier Martinez Canillas 提交于
IGEP-based boards can have two different flash memories, a OneNAND or a NAND device. Add a configuration option for to choose which memory to use. Signed-off-by: NJavier Martinez Canillas <javier@dowhile0.org> Acked-by: NEnric Balletbo i Serra <eballetbo@gmail.com>
-
由 Chandan Nath 提交于
This patch adds board-specific initialization for CPSW on TI AM335X based boards. Tested on BeagleBone. Signed-off-by: NChandan Nath <chandan.nath@ti.com> [Ilya: split board-specific part into separate patch] Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>
-
由 Ilya Yanok 提交于
Read the on-board EEPROM during startup to detect the version of the board we are running on (as for now only BeagleBone vs EVM detection is supported). Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>
-
由 Chandan Nath 提交于
This patch adds pin mux settings for CPSW switch found on TI AM335X based boards (MII and RGMII modes). Signed-off-by: NChandan Nath <chandan.nath@ti.com> [Ilya: split pinmux into separate patch] Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>
-
由 Chandan Nath 提交于
This patch adds platform-specific initialization for CPSW switch on TI AM33XX SoCs. Signed-off-by: NChandan Nath <chandan.nath@ti.com> [Ilya: split init out of original patch] Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>
-
由 Cyril Chemparathy 提交于
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas Instruments. This patch adds a simple driver (based on the Linux driver) for this hardware module. This patch also adds support to clean and flush dcache during packet send and receive. Changes by Sandhya: Added support to clean and flush dcache during packet send/receive and added timeouts. Signed-off-by: NCyril Chemparathy <cyril@ti.com> Signed-off-by: NChandan Nath <chandan.nath@ti.com> Signed-off-by: NSatyanarayana, Sandhya <sandhya.satyanarayana@ti.com> [Ilya: Cleaned cache handling, some style cleanup, some small fixes, use of internal RAM for descriptors] Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>
-
由 Peter Meerwald 提交于
Signed-off-by: NPeter Meerwald <p.meerwald@bct-electronic.com>
-
由 Mikhail Kshevetskiy 提交于
also fix NS16550_init() as we need 16x divider Signed-off-by: NMikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: NChristian Riesch <christian.riesch@omicron.at> Tested-by: NChristian Riesch <christian.riesch@omicron.at> Acked-by: NSughosh Ganu <urwithsughosh@gmail.com> Tested-by: NSughosh Ganu <urwithsughosh@gmail.com>
-
由 Mikhail Kshevetskiy 提交于
Signed-off-by: NMikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Tested-by: NSughosh Ganu <urwithsughosh@gmail.com>
-