am33xx: Document what we're doing with ddrctrl->ddrckectrl

- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.
Signed-off-by: NTom Rini <trini@ti.com>

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -170,10 +170,8 @@ void config_ddr(short ddr_type)
 
 		config_io_ctrl(&ioctrl);
 
-		writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
-				&ddrctrl->ddrioctrl);
-		writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
-				&ddrctrl->ddrckectrl);
+		/* Set CKE to be controlled by EMIF/DDR PHY */
+		writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
 		config_emif_ddr2();
 	}

arch/arm/include/asm/arch-am33xx/ddr_defs.h

@@ -28,6 +28,7 @@
 #define CMD_FORCE		0x00
 #define CMD_DELAY		0x00
 #define PHY_DLL_LOCK_DIFF	0x0
+#define DDR_CKE_CTRL_NORMAL	0x1
 
 #define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
 #define DDR2_EMIF_TIM1		0x0666B3C9