The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
driver, but the code that used that macro was removed over a year
ago, so board configuration files no longer need to define it.

The _IO_BASE macro is also automatically defined to 0 if it isn't
already set, so there's no need to define that macro either in the
board configuration files.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Acked-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: NAndy Fleming <afleming@freescale.com>
Acked-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

We want the outbound PCI memory map to end at the 4G boundary so we
can maximize the amount of space available for inbound mappings if
we have large amounts of memory.

This matches the device tree setup in the kernel for the 36-bit physical
configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.

The functionality of the individual commands is still available via
the 'i2c' command.

This change only has an impact on those boards which did not have
CONFIG_I2C_CMD_TREE defined.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map.  Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus.  We need
to use the new mapping functions to handle that read properly in the
36-bit config.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The eLBC only handles 32-bit physical address in systems with 36-bit
physical.  The previos generation of LBC handled 34-bit physical
address in 36-bit systems.  Added a new CONFIG option to convey
the difference between the LBC and eLBC.

Also added defines for XAM bits used in LBC for the extended 34-bit
support.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.

This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAndy Fleming <afleming@freescale.com>

Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAndy Fleming <afleming@freescale.com>

Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAndy Fleming <afleming@freescale.com>

Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAndy Fleming <afleming@freescale.com>

Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAndy Fleming <afleming@freescale.com>

This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define

 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE

but that's bogus and did not work anyhow.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.
Signed-off-by: NDave Liu <daveliu@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: NJon Loeliger <jdl@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>

The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: NDave Liu <daveliu@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: NJon Loeliger <jdl@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE).
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns
0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in
config file.

It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to
make room for the increased code size with NAND enabled.
Signed-off-by: NJason Jin <Jason.Jin@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndrew Fleming-AFLEMING <afleming@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndrew Fleming-AFLEMING <afleming@freescale.com>

Signed-off-by: NDave Liu <daveliu@freescale.com>

This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.
Signed-off-by: NLiu Yu <yu.liu@freescale.com>

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Commit 445a7b38 introduced the following
compile warnings:

cmd_i2c.c:112: warning: missing braces around initializer
cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
system information like mac addresses etc. This patch enables it.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out.  In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: NAndy Fleming <afleming@freescale.com>