As suggested by Grant Likely this patch enables the Xilinx SystemACE
driver to select 8 or 16bit mode upon startup.
Signed-off-by: NStefan Roese <sr@denx.de>

Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command
is fully finished. The sync() is defined in each CPU's io.h file. For
those CPUs which do not need sync for now, a dummy sync() is defined in
their io.h as well.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables the "new" get_dev() function for block devices
introduced by Grant Likely to be used on systems that still suffer
from the relocation problems (manual relocation neede because of
problems with linker script).

Hopefully we can resolve this relocation issue soon for all platform
so we don't need this additional code anymore.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch removes some problems when the Xilinx SystemACE driver
is used with 16bit access on an big endian platform (like the
AMCC Katmai).
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch switches to the desired I2C bus when the date/dtt
commands are called. This can be configured using the
CFG_RTC_BUS_NUM and/or CFG_DTT_BUS_NUM defines.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:

- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.
Signed-off-by: NStefan Roese <sr@denx.de>

Since the existing 4xx SPD SDRAM initialization routines for the
405 SDRAM controller and the 440 DDR controller don't have much in
common this patch splits both drivers into different files.

This is in preparation for the 440 DDR2 controller support (440SP/e).
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for multiple I2C busses on the PPC4xx
platforms. Define CONFIG_I2C_MULTI_BUS in the board config file
to make use of this feature.

It also merges the 405 and 440 i2c header files into one common
file 4xx_i2c.h.

Also the 4xx i2c reset procedure is reworked since I experienced
some problems with the first access on the 440SPe Katmai board.
Signed-off-by: NStefan Roese <sr@denx.de>

Block device read/write is anonymous data; there is no need to use a
typed pointer.  void * is fine.  Also add a hook for block_read functions
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Preparation for future patches which support block device writing
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Register read/write does not need to be wrapped in a full function.  The
patch replaces them with macros.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The code in this file is not a command; it is a device driver.  Put it in
the correct place.  There are zero functional changes in this patch, it
only moves the file.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch is in preparation of additional changes to the sysace driver.
May as well take this opportunity to fixup the inconsistent whitespace since
this file is about to undergo major changes anyway.

There are zero functional changes in this patch.  It only cleans up the
the whitespace.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

isprint is already defined in ctype.c
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Printing a buffer is a darn useful thing.  Move the buffer print code
into print_buffer() in lib_generic/
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Change the xilinx device drivers and board code to include config.h
instead of xparameters.h directly.  config.h always includes the
correct xparameters file.  This change reduces the posibility of
including the wrong file when adding a new xilinx board port
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Each of the filesystem drivers duplicate the get_dev routine.  This change
merges them into a single function in part.c
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

as root file system images.

Update / extend Software Update Mechanism for MCC200 board:

- Add support for rootfs image added. The environment variables
  "rootfs_st" and "rootfs_nd" can be used to override the default
  values of the image start and end.
- Remove excessive key check code.
- Code cleanup.

As spotted by Matthias Fuchs, the READY input should not be
enabled for the NOR FLASH on the Sequoia board.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Some boards that can have more than 768MBytes of SDRAM need to
set "initrd_high", so that the initrd can be accessed by the
Linux kernel.
Signed-off-by: NStefan Roese <sr@denx.de>

Previously the strapping DCR/SDR was read to determine if the internal PCI
arbiter is enabled or not. This strapping bit can be overridden, so now
the current status is read from the correct DCR/SDR register.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

When PCI PNP is enabled the pci pnp configuration routine is called
which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some
problems with some PCI cards. For now disable the PCI PNP configuration.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NReinhard Arlt <reinhard.arlt@esd-electronics.com>

Signed-off-by: NReinhard Arlt <reinhard.arlt@esd-electronics.com>

Signed-off-by: NStefan Roese <sr@denx.de>