Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OS
U-Boot.Mirror
提交
c105f4c6
U
U-Boot.Mirror
项目概览
OS
/
U-Boot.Mirror
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
U
U-Boot.Mirror
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
c105f4c6
编写于
1月 30, 2007
作者:
W
Wolfgang Denk
提交者:
Wolfgang Denk
1月 30, 2007
浏览文件
操作
浏览文件
下载
差异文件
Merge with /home/sr/git/u-boot/denx-merge-sr
上级
d526de33
e802594b
变更
10
隐藏空白更改
内联
并排
Showing
10 changed file
with
74 addition
and
945 deletion
+74
-945
Makefile
Makefile
+4
-1
board/amcc/yellowstone/Makefile
board/amcc/yellowstone/Makefile
+0
-51
board/amcc/yellowstone/config.mk
board/amcc/yellowstone/config.mk
+0
-44
board/amcc/yellowstone/init.S
board/amcc/yellowstone/init.S
+0
-112
board/amcc/yellowstone/u-boot.lds
board/amcc/yellowstone/u-boot.lds
+0
-157
board/amcc/yellowstone/yellowstone.c
board/amcc/yellowstone/yellowstone.c
+0
-549
board/amcc/yosemite/yosemite.c
board/amcc/yosemite/yosemite.c
+8
-0
include/configs/pdnb3.h
include/configs/pdnb3.h
+6
-5
include/configs/sequoia.h
include/configs/sequoia.h
+19
-9
include/configs/yosemite.h
include/configs/yosemite.h
+37
-17
未找到文件。
Makefile
浏览文件 @
c105f4c6
...
...
@@ -1236,7 +1236,10 @@ yosemite_config: unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx yosemite amcc
yellowstone_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx yellowstone amcc
@
mkdir
-p
$(obj)
include
@
echo
"#define CONFIG_YELLOWSTONE"
>
$(obj)
include/config.h
@
echo
"Configuring for yellowstone board as subset of yosemite..."
@
$(MKCONFIG)
-a
yosemite ppc ppc4xx yosemite amcc
yucca_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc ppc4xx yucca amcc
...
...
board/amcc/yellowstone/Makefile
已删除
100644 → 0
浏览文件 @
d526de33
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include
$(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.a
COBJS
=
$(BOARD)
.o
SOBJS
=
init.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
OBJS
:=
$(
addprefix
$(obj)
,
$(COBJS)
)
SOBJS
:=
$(
addprefix
$(obj)
,
$(SOBJS)
)
$(LIB)
:
$(OBJS) $(SOBJS)
$(AR)
$(ARFLAGS)
$@
$(OBJS)
clean
:
rm
-f
$(SOBJS)
$(OBJS)
distclean
:
clean
rm
-f
$(LIB)
core
*
.bak .depend
#########################################################################
# defines $(obj).depend target
include
$(SRCTREE)/rules.mk
sinclude
$(obj).depend
#########################################################################
board/amcc/yellowstone/config.mk
已删除
100644 → 0
浏览文件 @
d526de33
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq
($(ramsym),1)
TEXT_BASE
=
0xFBD00000
else
TEXT_BASE
=
0xFFF80000
endif
PLATFORM_CPPFLAGS
+=
-DCONFIG_440
=
1
ifeq
($(debug),1)
PLATFORM_CPPFLAGS
+=
-DDEBUG
endif
ifeq
($(dbcr),1)
PLATFORM_CPPFLAGS
+=
-DCFG_INIT_DBCR
=
0x8cff0000
endif
board/amcc/yellowstone/init.S
已删除
100644 → 0
浏览文件 @
d526de33
/*
*
*
See
file
CREDITS
for
list
of
people
who
contributed
to
this
*
project
.
*
*
This
program
is
free
software
; you can redistribute it and/or
*
modify
it
under
the
terms
of
the
GNU
General
Public
License
as
*
published
by
the
Free
Software
Foundation
; either version 2 of
*
the
License
,
or
(
at
your
option
)
any
later
version
.
*
*
This
program
is
distributed
in
the
hope
that
it
will
be
useful
,
*
but
WITHOUT
ANY
WARRANTY
; without even the implied warranty of
*
MERCHANTABILITY
or
FITNESS
FOR
A
PARTICULAR
PURPOSE
.
See
the
*
GNU
General
Public
License
for
more
details
.
*
*
You
should
have
received
a
copy
of
the
GNU
General
Public
License
*
along
with
this
program
; if not, write to the Free Software
*
Foundation
,
Inc
.
,
59
Temple
Place
,
Suite
330
,
Boston
,
*
MA
02111
-
1307
USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/*
General
*/
#define TLB_VALID 0x00000200
/*
Supported
page
sizes
*/
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/*
Storage
attributes
*/
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/*
Access
control
*/
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/*
Some
handy
macros
*/
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr
r1
;\
bl
0
f
;
#define tlbtab_end\
.
long
0
,
0
,
0
; \
0
:
mflr
r0
; \
mtlr
r1
; \
blr
;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.
long
TLB0
(
epn
,
sz
),
TLB1
(
rpn
,
erpn
),
TLB2
(
attr
)
/**************************************************************************
*
TLB
TABLE
*
*
This
table
is
used
by
the
cpu
boot
code
to
setup
the
initial
tlb
*
entries
.
Rather
than
make
broad
assumptions
in
the
cpu
source
tree
,
*
this
table
lets
each
board
set
things
up
however
they
like
.
*
*
Pointer
to
the
table
is
returned
in
r1
*
*************************************************************************/
.
section
.
bootpg
,
"ax"
.
globl
tlbtab
tlbtab
:
tlbtab_start
/
*
*
BOOT_CS
(
FLASH
)
must
be
first
.
Before
relocation
SA_I
can
be
off
to
use
the
*
speed
up
boot
process
.
It
is
patched
after
relocation
to
enable
SA_I
*/
tlbentry
(
CFG_BOOT_BASE_ADDR
,
SZ_256M
,
CFG_BOOT_BASE_ADDR
,
0
,
AC_R|AC_W|AC_X|SA_G/*|SA_I
*/)
/
*
TLB
-
entry
for
init
-
ram
in
dcache
(
SA_I
must
be
turned
off
!)
*/
tlbentry
(
CFG_INIT_RAM_ADDR
,
SZ_64K
,
CFG_INIT_RAM_ADDR
,
0
,
AC_R|AC_W|AC_X
|
SA_G
)
tlbentry
(
CFG_SDRAM_BASE
,
SZ_256M
,
CFG_SDRAM_BASE
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
CFG_PCI_BASE
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_NVRAM_BASE_ADDR
,
SZ_256M
,
CFG_NVRAM_BASE_ADDR
,
0
,
AC_R|AC_W|AC_X|SA_W|SA_I
)
/
*
PCI
*/
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
CFG_PCI_MEMBASE
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE1
,
SZ_256M
,
CFG_PCI_MEMBASE1
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE2
,
SZ_256M
,
CFG_PCI_MEMBASE2
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE3
,
SZ_256M
,
CFG_PCI_MEMBASE3
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
/
*
USB
2
.0
Device
*/
tlbentry
(
CFG_USB_DEVICE
,
SZ_1K
,
0x50000000
,
0
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
board/amcc/yellowstone/u-boot.lds
已删除
100644 → 0
浏览文件 @
d526de33
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yellowstone/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
board/amcc/yellowstone/yellowstone.c
已删除
100644 → 0
浏览文件 @
d526de33
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR
;
extern
flash_info_t
flash_info
[
CFG_MAX_FLASH_BANKS
];
/* info for FLASH chips */
int
board_early_init_f
(
void
)
{
register
uint
reg
;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr
(
ebccfga
,
xbcfg
);
reg
=
mfdcr
(
ebccfgd
);
mtdcr
(
ebccfgd
,
reg
|
0x04000000
);
/* Set ATC */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash size 64Meg. */
out32
(
GPIO0_OSRL
,
in32
(
GPIO0_OSRL
)
|
0x50010000
);
out32
(
GPIO0_TSRL
,
in32
(
GPIO0_TSRL
)
|
0x50010000
);
out32
(
GPIO0_ISR1L
,
in32
(
GPIO0_ISR1L
)
|
0x50000000
);
/*setup emac */
out32
(
GPIO0_TCR
,
in32
(
GPIO0_TCR
)
|
0xC080
);
out32
(
GPIO0_TSRL
,
in32
(
GPIO0_TSRL
)
|
0x40
);
out32
(
GPIO0_ISR1L
,
in32
(
GPIO0_ISR1L
)
|
0x55
);
out32
(
GPIO0_OSRH
,
in32
(
GPIO0_OSRH
)
|
0x50004000
);
out32
(
GPIO0_ISR1H
,
in32
(
GPIO0_ISR1H
)
|
0x00440000
);
/*UART1 */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
|
0x02000000
);
out32
(
GPIO1_OSRL
,
in32
(
GPIO1_OSRL
)
|
0x00080000
);
out32
(
GPIO1_ISR2L
,
in32
(
GPIO1_ISR2L
)
|
0x00010000
);
/* external interrupts IRQ0...3 */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
&
~
0x00f00000
);
out32
(
GPIO1_TSRL
,
in32
(
GPIO1_TSRL
)
&
~
0x0000ff00
);
out32
(
GPIO1_ISR1L
,
in32
(
GPIO1_ISR1L
)
|
0x00005500
);
#if 0 /* test-only */
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr
(
uic0sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic0er
,
0x00000000
);
/* disable all */
mtdcr
(
uic0cr
,
0x00000009
);
/* ATI & UIC1 crit are critical */
mtdcr
(
uic0pr
,
0xfffffe13
);
/* per ref-board manual */
mtdcr
(
uic0tr
,
0x01c00008
);
/* per ref-board manual */
mtdcr
(
uic0vr
,
0x00000001
);
/* int31 highest, base=0x000 */
mtdcr
(
uic0sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic1sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic1er
,
0x00000000
);
/* disable all */
mtdcr
(
uic1cr
,
0x00000000
);
/* all non-critical */
mtdcr
(
uic1pr
,
0xffffe0ff
);
/* per ref-board manual */
mtdcr
(
uic1tr
,
0x00ffc000
);
/* per ref-board manual */
mtdcr
(
uic1vr
,
0x00000001
);
/* int31 highest, base=0x000 */
mtdcr
(
uic1sr
,
0xffffffff
);
/* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr
(
sdr_pci0
,
reg
);
mtsdr
(
sdr_pci0
,
0x80000000
|
reg
);
/* PCI arbiter enabled */
mtsdr
(
sdr_pfc0
,
0x00003e00
);
/* Pin function */
mtsdr
(
sdr_pfc1
,
0x00048000
);
/* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x04
)
=
0x00
;
/*enable ethernet */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x08
)
=
0xf0
;
#if 0 /* test-only */
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
#endif
/*get rid of flash write protect */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x07
)
=
0x00
;
return
0
;
}
int
misc_init_r
(
void
)
{
uint
pbcr
;
int
size_val
=
0
;
/* Re-do sizing to get full correct info */
mtdcr
(
ebccfga
,
pb0cr
);
pbcr
=
mfdcr
(
ebccfgd
);
switch
(
gd
->
bd
->
bi_flashsize
)
{
case
1
<<
20
:
size_val
=
0
;
break
;
case
2
<<
20
:
size_val
=
1
;
break
;
case
4
<<
20
:
size_val
=
2
;
break
;
case
8
<<
20
:
size_val
=
3
;
break
;
case
16
<<
20
:
size_val
=
4
;
break
;
case
32
<<
20
:
size_val
=
5
;
break
;
case
64
<<
20
:
size_val
=
6
;
break
;
case
128
<<
20
:
size_val
=
7
;
break
;
}
pbcr
=
(
pbcr
&
0x0001ffff
)
|
gd
->
bd
->
bi_flashstart
|
(
size_val
<<
17
);
mtdcr
(
ebccfga
,
pb0cr
);
mtdcr
(
ebccfgd
,
pbcr
);
/* adjust flash start and offset */
gd
->
bd
->
bi_flashstart
=
0
-
gd
->
bd
->
bi_flashsize
;
gd
->
bd
->
bi_flashoffset
=
0
;
/* Monitor protection ON by default */
(
void
)
flash_protect
(
FLAG_PROTECT_SET
,
-
CFG_MONITOR_LEN
,
0xffffffff
,
&
flash_info
[
0
]);
return
0
;
}
int
checkboard
(
void
)
{
char
*
s
=
getenv
(
"serial#"
);
u8
rev
;
u8
val
;
printf
(
"Board: Yellowstone - AMCC PPC440GR Evaluation Board"
);
rev
=
*
(
u8
*
)(
CFG_CPLD
+
0
);
val
=
*
(
u8
*
)(
CFG_CPLD
+
5
)
&
0x01
;
printf
(
", Rev. %X, PCI=%d MHz"
,
rev
,
val
?
66
:
33
);
if
(
s
!=
NULL
)
{
puts
(
", serial# "
);
puts
(
s
);
}
putc
(
'\n'
);
return
(
0
);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
#define NUM_TRIES 64
#define NUM_READS 10
void
sdram_tr1_set
(
int
ram_address
,
int
*
tr1_value
)
{
int
i
;
int
j
,
k
;
volatile
unsigned
int
*
ram_pointer
=
(
unsigned
int
*
)
ram_address
;
int
first_good
=
-
1
,
last_bad
=
0x1ff
;
unsigned
long
test
[
NUM_TRIES
]
=
{
0x00000000
,
0x00000000
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0x00000000
,
0x00000000
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0x00000000
,
0x00000000
,
0xFFFFFFFF
,
0xFFFFFFFF
,
0x00000000
,
0x00000000
,
0xAAAAAAAA
,
0xAAAAAAAA
,
0x55555555
,
0x55555555
,
0xAAAAAAAA
,
0xAAAAAAAA
,
0x55555555
,
0x55555555
,
0x55555555
,
0x55555555
,
0xAAAAAAAA
,
0xAAAAAAAA
,
0x55555555
,
0x55555555
,
0xAAAAAAAA
,
0xAAAAAAAA
,
0xA5A5A5A5
,
0xA5A5A5A5
,
0x5A5A5A5A
,
0x5A5A5A5A
,
0xA5A5A5A5
,
0xA5A5A5A5
,
0x5A5A5A5A
,
0x5A5A5A5A
,
0x5A5A5A5A
,
0x5A5A5A5A
,
0xA5A5A5A5
,
0xA5A5A5A5
,
0x5A5A5A5A
,
0x5A5A5A5A
,
0xA5A5A5A5
,
0xA5A5A5A5
,
0xAA55AA55
,
0xAA55AA55
,
0x55AA55AA
,
0x55AA55AA
,
0xAA55AA55
,
0xAA55AA55
,
0x55AA55AA
,
0x55AA55AA
,
0x55AA55AA
,
0x55AA55AA
,
0xAA55AA55
,
0xAA55AA55
,
0x55AA55AA
,
0x55AA55AA
,
0xAA55AA55
,
0xAA55AA55
};
/* go through all possible SDRAM0_TR1[RDCT] values */
for
(
i
=
0
;
i
<=
0x1ff
;
i
++
)
{
/* set the current value for TR1 */
mtsdram
(
mem_tr1
,
(
0x80800800
|
i
));
/* write values */
for
(
j
=
0
;
j
<
NUM_TRIES
;
j
++
)
{
ram_pointer
[
j
]
=
test
[
j
];
/* clear any cache at ram location */
__asm__
(
"dcbf 0,%0"
:
:
"r"
(
&
ram_pointer
[
j
]));
}
/* read values back */
for
(
j
=
0
;
j
<
NUM_TRIES
;
j
++
)
{
for
(
k
=
0
;
k
<
NUM_READS
;
k
++
)
{
/* clear any cache at ram location */
__asm__
(
"dcbf 0,%0"
:
:
"r"
(
&
ram_pointer
[
j
]));
if
(
ram_pointer
[
j
]
!=
test
[
j
])
break
;
}
/* read error */
if
(
k
!=
NUM_READS
)
{
break
;
}
}
/* we have a SDRAM0_TR1[RDCT] that is part of the window */
if
(
j
==
NUM_TRIES
)
{
if
(
first_good
==
-
1
)
first_good
=
i
;
/* found beginning of window */
}
else
{
/* bad read */
/* if we have not had a good read then don't care */
if
(
first_good
!=
-
1
)
{
/* first failure after a good read */
last_bad
=
i
-
1
;
break
;
}
}
}
/* return the current value for TR1 */
*
tr1_value
=
(
first_good
+
last_bad
)
/
2
;
}
void
sdram_init
(
void
)
{
register
uint
reg
;
int
tr1_bank1
,
tr1_bank2
;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram
(
mem_uabba
,
0x00000000
);
/* ubba=0 (default) */
mtsdram
(
mem_slio
,
0x00000000
);
/* rdre=0 wrre=0 rarw=0 */
mtsdram
(
mem_devopt
,
0x00000000
);
/* dll=0 ds=0 (normal) */
mtsdram
(
mem_clktr
,
0x40000000
);
/* ?? */
mtsdram
(
mem_wddctr
,
0x40000000
);
/* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram
(
mem_cfg0
,
0x00000000
);
/* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram
(
mem_b0cr
,
0x000a4001
);
/* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram
(
mem_b1cr
,
0x080a4001
);
/* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram
(
mem_tr0
,
0x410a4012
);
/* ?? */
mtsdram
(
mem_rtr
,
0x04080000
);
/* ?? */
mtsdram
(
mem_cfg1
,
0x00000000
);
/* Self-refresh exit, disable PM */
mtsdram
(
mem_cfg0
,
0x30000000
);
/* Disable EEC */
udelay
(
400
);
/* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram
(
mem_cfg0
,
0x80000000
);
/* Enable */
for
(;;)
{
mfsdram
(
mem_mcsts
,
reg
);
if
(
reg
&
0x80000000
)
break
;
}
sdram_tr1_set
(
0x00000000
,
&
tr1_bank1
);
sdram_tr1_set
(
0x08000000
,
&
tr1_bank2
);
mtsdram
(
mem_tr1
,
(((
tr1_bank1
+
tr1_bank2
)
/
2
)
|
0x80800800
)
);
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long
int
initdram
(
int
board
)
{
sdram_init
();
return
CFG_SDRAM_BANKS
*
(
CFG_KBYTES_SDRAM
*
1024
);
/* return bytes */
}
#if defined(CFG_DRAM_TEST)
int
testdram
(
void
)
{
unsigned
long
*
mem
=
(
unsigned
long
*
)
0
;
const
unsigned
long
kend
=
(
1024
/
sizeof
(
unsigned
long
));
unsigned
long
k
,
n
;
mtmsr
(
0
);
for
(
k
=
0
;
k
<
CFG_KBYTES_SDRAM
;
++
k
,
mem
+=
(
1024
/
sizeof
(
unsigned
long
)))
{
if
((
k
&
1023
)
==
0
)
{
printf
(
"%3d MB
\r
"
,
k
/
1024
);
}
memset
(
mem
,
0xaaaaaaaa
,
1024
);
for
(
n
=
0
;
n
<
kend
;
++
n
)
{
if
(
mem
[
n
]
!=
0xaaaaaaaa
)
{
printf
(
"SDRAM test fails at: %08x
\n
"
,
(
uint
)
&
mem
[
n
]);
return
1
;
}
}
memset
(
mem
,
0x55555555
,
1024
);
for
(
n
=
0
;
n
<
kend
;
++
n
)
{
if
(
mem
[
n
]
!=
0x55555555
)
{
printf
(
"SDRAM test fails at: %08x
\n
"
,
(
uint
)
&
mem
[
n
]);
return
1
;
}
}
}
printf
(
"SDRAM test passes
\n
"
);
return
0
;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
addr
;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
sdr_amp1
,
addr
);
mtsdr
(
sdr_amp1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
plb3_acr
);
mtdcr
(
plb3_acr
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
sdr_amp0
,
addr
);
mtsdr
(
sdr_amp0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
plb4_acr
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
plb4_acr
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
plb0_acr
)
&
~
plb0_acr_ppm_mask
)
|
plb0_acr_ppm_fair
;
addr
=
(
addr
&
~
plb0_acr_hbu_mask
)
|
plb0_acr_hbu_enabled
;
addr
=
(
addr
&
~
plb0_acr_rdp_mask
)
|
plb0_acr_rdp_4deep
;
addr
=
(
addr
&
~
plb0_acr_wrp_mask
)
|
plb0_acr_wrp_2deep
;
mtdcr
(
plb0_acr
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
plb1_acr
)
&
~
plb1_acr_ppm_mask
)
|
plb1_acr_ppm_fair
;
addr
=
(
addr
&
~
plb1_acr_hbu_mask
)
|
plb1_acr_hbu_enabled
;
addr
=
(
addr
&
~
plb1_acr_rdp_mask
)
|
plb1_acr_rdp_4deep
;
addr
=
(
addr
&
~
plb1_acr_wrp_mask
)
|
plb1_acr_wrp_2deep
;
mtdcr
(
plb1_acr
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIX0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIX0_PMM0LA
,
CFG_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIX0_PMM0PCILA
,
CFG_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIX0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIX0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIX0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIX0_PMM1LA
,
CFG_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIX0_PMM1PCILA
,
CFG_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIX0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIX0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIX0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIX0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIX0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIX0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CFG_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CFG_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int
is_pci_host
(
struct
pci_controller
*
hose
)
{
/* Bamboo is always configured as host. */
return
(
1
);
}
#endif
/* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void
hw_watchdog_reset
(
void
)
{
}
#endif
void
board_reset
(
void
)
{
/* give reset to BCSR */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x06
)
=
0x09
;
}
board/amcc/yosemite/yosemite.c
浏览文件 @
c105f4c6
...
...
@@ -65,12 +65,14 @@ int board_early_init_f(void)
out32
(
GPIO1_TSRL
,
in32
(
GPIO1_TSRL
)
&
~
0x0000ff00
);
out32
(
GPIO1_ISR1L
,
in32
(
GPIO1_ISR1L
)
|
0x00005500
);
#ifdef CONFIG_440EP
/*setup USB 2.0 */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
|
0xc0000000
);
out32
(
GPIO1_OSRL
,
in32
(
GPIO1_OSRL
)
|
0x50000000
);
out32
(
GPIO0_TCR
,
in32
(
GPIO0_TCR
)
|
0xf
);
out32
(
GPIO0_OSRH
,
in32
(
GPIO0_OSRH
)
|
0xaa
);
out32
(
GPIO0_ISR2H
,
in32
(
GPIO0_ISR2H
)
|
0x00000500
);
#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
...
...
@@ -105,8 +107,10 @@ int board_early_init_f(void)
/*enable ethernet */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x08
)
=
0xf0
;
#ifdef CONFIG_440EP
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x09
)
=
0x00
;
#endif
/*get rid of flash write protect */
*
(
unsigned
char
*
)(
CFG_BCSR_BASE
|
0x07
)
=
0x00
;
...
...
@@ -171,7 +175,11 @@ int checkboard(void)
u8
rev
;
u8
val
;
#ifdef CONFIG_440EP
printf
(
"Board: Yosemite - AMCC PPC440EP Evaluation Board"
);
#else
printf
(
"Board: Yellowstone - AMCC PPC440GR Evaluation Board"
);
#endif
rev
=
*
(
u8
*
)(
CFG_CPLD
+
0
);
val
=
*
(
u8
*
)(
CFG_CPLD
+
5
)
&
0x01
;
...
...
include/configs/pdnb3.h
浏览文件 @
c105f4c6
/*
* (C) Copyright 2006
* (C) Copyright 2006
-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Configuation settings for the PDNB3 board.
...
...
@@ -237,18 +237,19 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
#if defined(CONFIG_SCPU)
#define CFG_ENV_SECT_SIZE 0x20000
/* size of one complete sector */
/* no redundant environment on SCPU */
#define CFG_ENV_SECT_SIZE 0x20000
/* size of one complete sector */
#define CFG_ENV_SIZE 0x4000
/* Total Size of Environment Sector */
#else
#define CFG_ENV_SECT_SIZE 0x1000
/* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x1000
/* size of one complete sector
*/
#define CFG_ENV_SIZE 0x1000
/* Total Size of Environment Sector */
#endif
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#if !defined(CONFIG_SCPU)
/*
...
...
include/configs/sequoia.h
浏览文件 @
c105f4c6
/*
* (C) Copyright 2006
* (C) Copyright 2006
-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
...
...
@@ -23,7 +23,7 @@
*/
/************************************************************************
* sequoia.h - configuration for Sequoia
board (PowerPC440EPx)
* sequoia.h - configuration for Sequoia
& Rainier boards
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
...
...
@@ -31,7 +31,7 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)
*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)
*/
#ifndef CONFIG_RAINIER
#define CONFIG_SEQUOIA 1
/* Board is Sequoia */
#define CONFIG_440EPX 1
/* Specific PPC440EPx */
...
...
@@ -39,7 +39,7 @@
#define CONFIG_440GRX 1
/* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1
/* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33
333333
/* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 33
000000
/* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1
/* Call misc_init_r */
...
...
@@ -222,9 +222,21 @@
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_RAINIER
#define CONFIG_HOSTNAME sequoia
#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME rainier
#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
"hostname=sequoia\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
...
...
@@ -238,13 +250,11 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/sequoia/uImage\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp
100000 /tftpboot/sequoia
/u-boot.bin\0" \
"load=tftp
200000 /tftpboot/${hostname}
/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b
1
00000 FFFA0000 60000\0" \
"cp.b
2
00000 FFFA0000 60000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
...
...
include/configs/yosemite.h
浏览文件 @
c105f4c6
/*
* (C) Copyright 2005-200
6
* (C) Copyright 2005-200
7
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
...
...
@@ -22,7 +22,7 @@
*/
/************************************************************************
* yosemite.h - configuration for Y
OSEMITE board
* yosemite.h - configuration for Y
osemite & Yellowstone boards
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
...
...
@@ -30,9 +30,16 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1
/* Board is Yosemite */
#define CONFIG_440EP 1
/* Specific PPC440EP support */
#define CONFIG_4xx 1
/* ... PPC4xx family */
/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_YOSEMITE 1
/* Board is Yosemite */
#define CONFIG_440EP 1
/* Specific PPC440EP support */
#define CONFIG_HOSTNAME yosemite
#else
#define CONFIG_440GR 1
/* Specific PPC440GR support */
#define CONFIG_HOSTNAME yellowstone
#endif
#define CONFIG_4xx 1
/* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666
/* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1
/* Call board_early_init_f */
...
...
@@ -159,9 +166,21 @@
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_HOSTNAME yosemite
#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME yellowstone
#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
"hostname=yosemite\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
...
...
@@ -175,13 +194,12 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
"bootfile=/tftpboot/${hostname}/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp
100000 /tftpboot/yosemite
/u-boot.bin\0" \
"load=tftp
200000 /tftpboot/${hostname}
/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b
1
00000 fff80000 80000;" \
"cp.b
2
00000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
...
...
@@ -218,9 +236,15 @@
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*
Comment this out to enable USB 1.1 device
*/
/*
Comment this out to enable USB 1.1 device
*/
#define USB_2_0_DEVICE
#endif
/*CONFIG_440EP*/
#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
#define CONFIG_SUPPORT_VFAT
#else
#define CMD_USB 0
/* no USB on 440GR */
#endif
/* CONFIG_440EP */
#ifdef DEBUG
#define CONFIG_PANIC_HANG
...
...
@@ -243,11 +267,7 @@
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FAT | \
CFG_CMD_EXT2 | \
CFG_CMD_USB )
#define CONFIG_SUPPORT_VFAT
CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录