- 18 6月, 2015 3 次提交
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由 Jeroen Hofstee 提交于
Since the tam3517 base board has a 16bit wide nand connected to the gpmc, enable the prefetch mode, since that is now supported. Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: pekon gupta <pekon@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Daniel Mack <zonque@gmail.com> Cc: Tapani Utriainen <tapani@technexion.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jeroen Hofstee 提交于
commit c316f577 "mtd: OMAP: Enable GPMC prefetch mode" only enabled prefetch mode for 8 bit nand access, this adds 16 bit as well. Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Daniel Mack <zonque@gmail.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jeroen Hofstee 提交于
The prefech mode is a feature of the gpmc, not the ELM. An am3517 does not have an elm, but can do prefeches, so move the code out of the CONFIG_NAND_OMAP_ELM ifdef. Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Daniel Mack <zonque@gmail.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 17 6月, 2015 4 次提交
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由 Karsten Merker 提交于
The MSI Primo 81 is an Allwinner A31s-based tablet on which the OTG port is the only accessible USB interface. The existing defconfig had VGA console on the LCD enabled, but was missing keyboard support because the prerequisites for that (sunxi MUSB support and AXP221 GPIO support) had not been available before. All previously missing dependencies are available now, so this patch enables keyboard support and its prerequisites in the defconfig. Signed-off-by: NKarsten Merker <merker@debian.org> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
Currently on sun6i after a "reset" the prompt returns and the user can even type stuff until the watchdog triggers and does the actual reset. This is somewhat unexpected behavior for the "reset" command, this commit adds an endless loop to wait for the watchdog to trigger so that we do not return to the prompt. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
Remove the unused sunxi_musb_exit method, there is no code in u-boot calling the exit method, and our implementation was broken as it did not disable the clocks and asserted reset. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
Fully resetting the controller is a too big hammer, and the musb_core will then afterwards fail to communicate with any endpoints other then 0 as too much state was cleared. Instead report vbus low for 200ms which will effectively end the current session without needing to do a full reset. This fixes usb mass-storage devices no longer working after a "usb reset" Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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- 16 6月, 2015 1 次提交
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- 15 6月, 2015 13 次提交
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由 Tom Rini 提交于
In the cases where we make use of environment in SPL we do not need these defaults compiled in and available. These are taking up space that in some cases now prevent linking, so drop. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Yegor Yefremov 提交于
Vision Systems's Baltos is based on AM335x SoC from Texas Instruments. This patch adds support such Industrial PCs in mainline u-boot. [ balbi@ti.com: updated original patch to current u-boot ] Signed-off-by: NYegor Yefremov <yegorslists@googlemail.com> Signed-off-by: NFelipe Balbi <balbi@ti.com>
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由 Lokesh Vutla 提交于
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Masahiro Yamada 提交于
Now all the AVR32 boards have been converted into Generic Board. Select it in Kconfig and clean up defines in header files. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Lokesh Vutla 提交于
On AM437x-GP Evm there is 2GB of DDR3 memory available as stated in AM437x GP EVM HardwareUser's guide http://www.ti.com/lit/ug/spruhw7/spruhw7.pdf. But MAX_RAM_BANK_SIZE is defined as 1GB. Fixing MAX_RAM_BANK_SIZE to 2GB on AM43xx. Reported-by: NShivasharan Nagalikar <shivasharan.nagalikar@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: NYan Liu <yan-liu@ti.com> Signed-off-by: NTom Rini <trini@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Enable booting from NAND on the am437xx-evm. Signed-off-by: NTom Rini <trini@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Roger Quadros 提交于
Use the correct partition names from with the Device Tree blob and the kernel is picked up. Also use partition name instead of number for the root filesystem in the kernel boot arguments. Signed-off-by: NRoger Quadros <rogerq@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Roger Quadros 提交于
We almost always use UBIFS for user accessible NAND file systems and the UBIFS file system might contain more than one volume within the single NAND partition. The last NAND partition is therefore more appropriately named as "NAND.file-system" instead of "NAND.rootfs" The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the last NAND partition. This patch makes the partition name consistent between u-boot and the kernel. Signed-off-by: NRoger Quadros <rogerq@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Roger Quadros 提交于
AM43xx EVMs have NAND so enable it. Signed-off-by: NRoger Quadros <rogerq@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Mark Langsdorf 提交于
The Calxeda highbank SOC needs a custom sequence to bring up SATA links, so override ahci_link_up with custom function to handle combophy setup. Signed-off-by: NMark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Richard Gibbs Signed-off-by: NRob Herring <robh@kernel.org> Signed-off-by: NAndre Przywara <osp@andrep.de>
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- 14 6月, 2015 4 次提交
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由 Stefan Roese 提交于
To support the Armada 38x, new values for the request-delay and the response-timeout are needed. As the values already implemented in this tool (for Kirkwood and Armada XP) don't seem to work here. To make this more flexible, lets add make those 2 parameters configurable via the cmdline. Here the new parameters: -q <req-delay>: use specific request-delay -s <resp-timeo>: use specific response-timeout For the Marvell DB-88F6820 these values are known to work: One board: -q 2 -s 1 2nd board: -q 5 -s 5 So this seems to be even board specific. But with this patch now those values can be specified and tested via the cmdline. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Kevin Smith 提交于
SMP-enabled Linux kernels read the CBAR register in CP15 to find the address of the SCU registers. After remapping internal registers, also update the CBAR so the kernel can find them. Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com> Acked-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
L2 cache may still be enabled by the BootROM. We need to first disable it before enabling d-cache support. Signed-off-by: NStefan Roese <sr@denx.de> Tested-by: NKevin Smith <kevin.smith@elecsyscorp.com>
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由 Kevin Smith 提交于
If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board to specify the offset of the payload image into the kwb image file. This value was being used to locate the image, but was not used in the "header size" field of the main header. Move the use of this macro into the function that returns the header size so that the same value is used in all places. Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com> Tested-by: NStefan Roese <sr@denx.de>
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- 13 6月, 2015 15 次提交
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由 Mark Langsdorf 提交于
The AHCI driver currently waits 5s before timing out when sending a data command to a drive. Some drives take upwards of 8s to respond to the initial data command while they're spinning up. Increase the data io timeout to 10s so that those drives can be found on initial scsi scan. Signed-off-by: NMark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: NAndre Przywara <osp@andrep.de>
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由 Mark Langsdorf 提交于
Enable full 48-bit LBA48 data reads by passing the upper word of the LBA block pointer in bytes 9 and 10 of the FIS. This allows uboot to load data from any arbitrary sector on a drive with 2 or more TB of available data connected to an AHCI controller. Signed-off-by: NMark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: NAndre Przywara <osp@andrep.de> [trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop warnings on platforms that don't enable that feature ] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Mark Langsdorf 提交于
Signed-off-by: NMark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: NAndre Przywara <osp@andrep.de>
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由 Mark Langsdorf 提交于
The Calxeda Midway part has A15 cores, which do not have the Highbank A9's SCU used there for resetting the chip. Add code to distinguish between the A9 and the A15 and invoke the appropriate register writes to support the newer part. Andre: rework detection of Highbank vs. Midway Rob: fix Andre's reworked detection Signed-off-by: NMark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: NAndre Przywara <osp@andrep.de> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Rob Herring 提交于
Andre: assign names to the magic values Signed-off-by: NRob Herring <robh@kernel.org> Signed-off-by: NAndre Przywara <osp@andrep.de>
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由 Lokesh Vutla 提交于
Adding the mux data, manual and virtual mode settings for BeagleBoard-X15. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Lokesh Vutla 提交于
Enable IO delay recalibration sequence. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Nishanth Menon 提交于
Adding the mux data, manual and virtual mode settings for DRA7-evm. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NVishal Mahaveer <vishalm@ti.com>
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由 Lokesh Vutla 提交于
Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Lokesh Vutla 提交于
do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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