- 07 5月, 2018 1 次提交
-
-
由 Tom Rini 提交于
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 02 5月, 2018 3 次提交
-
-
由 Hannes Schmelzer 提交于
The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this quirk is to tell the sdhci-driver that the IP-core doesn't have a "high- speed-enable" bit in its registers. With this commit we change this to the correct quirk: SDHCI_QUIRK_BROKEN_HISPD_MODE Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
-
由 Hannes Schmelzer 提交于
Some IP-core implementations of the SDHCI have different troubles on the silicon where they are placed. On ZYNQ platform for example Xilinx doesn't accept the hold timing of an eMMC chip which operates in High-Speed mode and must be forced to operate in non high-speed mode. To get rid of this "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced. For more details about this refer to the Xilinx answer-recor #59999 https://www.xilinx.com/support/answers/59999.html This commit: - doesn't set HISPD bit on the host-conroller - reflects this fact within the host-controller capabilities Upon this the layer above (mmc-driver) can setup the card correctly. Otherwise the MMC card will be switched into high-speed mode and causes possible timing violation on the host-controller side. Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at> Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
-
由 Peng Fan 提交于
sd_read_ssr returns 0, means no error. Fixes: 5b2e72f3("mmc: read ssr only if MMC write support is enabled") Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
-
- 28 4月, 2018 1 次提交
-
-
由 Tom Rini 提交于
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 25 4月, 2018 1 次提交
-
-
由 Philipp Tomsich 提交于
Throughput tests have shown the sunxi_mmc driver to take over 10s to read 10MB from a fast eMMC device due to excessive delays in polling loops. This commit restructures the main polling loops to use get_timer(...) to determine whether a (millisecond) timeout has expired. We choose not to use the wait_bit function, as we don't need interruptability with ctrl-c and have at least one case where two bits (one for an error condition and another one for completion) need to be read and using wait_bit would have not added to the clarity. The observed speedup in testing on a A31 is greater than 10x (e.g. a 10MB write decreases from 9.302s to 0.884s). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com> Tested-by: NMylène Josserand <mylene.josserand@bootlin.com> Acked-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NTom Rini <trini@konsulko.com>
-
- 24 4月, 2018 1 次提交
-
-
由 Marek Vasut 提交于
Staticize the function since it's only used in mmc.c . Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Tom Rini <trini@konsulko.com>
-
- 23 4月, 2018 4 次提交
-
-
由 Masahiro Yamada 提交于
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig. When booting from SD/eMMC, obviously its clock has been properly set up by the boot ROM. Acutually, no need to re-initialize the clock in SPL. Using a clock driver would generalize the SoC specific code, but solving the memory footprint problem would win. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
-
由 Masahiro Yamada 提交于
I need to differentiate the clock handling for uniphier-sd. Move it to each driver's probe function from the tmio common code so that renesas-sdhi will not be affected. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
-
由 Heinrich Schuchardt 提交于
The Odroid C2 fails to read from mmc with U-Boot v2018.03. The change avoids a division by zero. The fix was suggested by Jaehoon in https://lists.denx.de/pipermail/u-boot/2018-January/318577.htmlReported-by: NVagrant Cascadian <vagrant@debian.org> Suggested-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: NVagrant Cascadian <vagrant@debian.org>
-
由 Stefan Mavrodiev 提交于
U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where PLL5 is used, with clock rates respectively 600MHz and 768MHz. Thus there are different phase degree steps - 24 for the kernel and 30 for u-boot. In the kernel driver the phase is set 90 deg for output and 120 for sample. Dividing by 30 will result values 3 and 4. Those are the values set in the u-boot driver. However, the condition defining delays is wrong. MMC core driver requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but phase is set 30 deg for output and 120 deg for sample. Apparently this works for most cards. On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains about it. Maybe there is other boards with similar problem? So the fix is to match delays for both u-boot and kernel. Signed-off-by: NStefan Mavrodiev <stefan@olimex.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
-
- 22 4月, 2018 2 次提交
-
-
由 Marek Vasut 提交于
Add Kconfig entry for SH MMCIF driver. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
-
由 Marek Vasut 提交于
Add MMC DM and DT probing support into the SH MMCIF driver. This patch abstracts out the common bits of the send command and set ios functions, so they can be used both by DM and non DM setups and adds the DM probe support. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
-
- 17 4月, 2018 1 次提交
-
-
由 Matt Pelland 提交于
The mv_sdhci driver was not zeroing the sdhci_host structure it allocates causing random access violations in parts of the mmc core where the "ops" member pointers are checked and called if not NULL. Signed-off-by: NMatt Pelland <mpelland@starry.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
- 14 4月, 2018 1 次提交
-
-
由 Marek Vasut 提交于
Synchronize the naming with Linux, call the common code TMIO. No functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
- 12 4月, 2018 21 次提交
-
-
由 Marek Vasut 提交于
The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants of the IP. There is no DT property which allows discerning those, so what Linux does is it checks the size of the register area and if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle the distinction the same way. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Add support for 16bit mutation of the Matsushita SD IP. Since some registers are internally 32bit, the matsu_sd_{read,write}l() has to special-case this 16bit variant a bit. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Drop useless check in matsu_sd_{read,write}q(), this is only ever called to read the data from FIFO and only when 64bit variant of the block is used anyway. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Add macros to generate the FIFO accessors, since the code is almost the same with only minor differences. This is done in preparation for adding 16bit variant of the IP. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Add Kconfig entry for the Renesas SDHI variant of the controller and split the Makefile entries accordingly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
由 Marek Vasut 提交于
Factor out common code from the uniphier SD driver, change the prefix of the functions from uniphier_sd_ to matsu_sd_ and create separate renesas-sdhi.c driver. Thus far, all the code is still compiled when CONFIG_UNIPHIER_MMC is selected and there is no functional change. This patch is a preparation for further split of the SoC specific parts of the Matsushita SD driver, used both on Uniphier and R-Car. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
-
- 09 4月, 2018 1 次提交
-
-
由 Mario Six 提交于
Migrate the CONFIG_FSL_ESDHC option to Kconfig. Signed-off-by: NMario Six <mario.six@gdsys.cc>
-
- 05 4月, 2018 1 次提交
-
-
由 Jonathan Gray 提交于
In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and later start.elf now sets the EMMC clock to 200 MHz. According to Phil Elwell in https://github.com/raspberrypi/firmware/issues/953 the SDHost controller shares the core/VPU clock and doesn't use the EMMC clock. Use the core clock id when determining the frequency to allow U-Boot to work with recent versions of raspberrypi-firmware. Otherwise U-Boot hangs at: U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100) DRAM: 948 MiB RPI 3 Model B (0xa02082) MMC: mmc@7e202000: 0, sdhci@7e300000: 1 Loading Environment from FAT... Signed-off-by: NJonathan Gray <jsg@jsg.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
-
- 30 3月, 2018 2 次提交
-
-
由 Bernhard Messerklinger 提交于
Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: NBernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Rick Chen 提交于
nsd32_mmc was created to support ftsdc010 dm. It is not necessary to separate both, so merge it to ftsdc010. Signed-off-by: NRick Chen <rick@andestech.com> Signed-off-by: NRick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
-