Allow sending restart conditions upon direction change as this is
required by some chips.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NHeiko Schocher <hs@denxx.de>

This converts the following to Kconfig:
   CONFIG_SYS_I2C_OMAP24XX
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NNadav Haklai <nadavh@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.

Issue:
Wrong base address is assigned to MDIO interface during probe.

Fix:
Get MDIO address from PHY handler parent base address.

This should be refined in the future when MDIO driver is implemented.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.
Signed-off-by: NStefan Chulski <stefanc@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NKostya Porotchkin <kostap@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Increase env sector size from 64kb to 256kb for qspi boot.
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Acked-by: NPriyanka Jain <priyanka.jain@nxp.com>
Acked-by: NYogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

IFC and QSPI are muxed on board. Add fsl_fdt_fixup_flash() to disable
IFC node in dts if QSPI is enabled, or disable QSPI node in dts if
otherwise.
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NRajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Nyinbo.zhu <yinbo.zhu@nxp.com>
[YS: Revise subject, remove commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

We shouldn't always change the status to okay.  There could be
situations that the esdhc is intentionally disabled in the device
tree.
Signed-off-by: NLi Yang <leoyang.li@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This bug is brought by the commit 3d8553f0 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise subject and commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch enables driver model for USB in defconfigs for LS1021A
platforms.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Function enable_layerscape_ns_access() is alreayd called soc-wide.
Remove duplicated calling from individual boards.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Add commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Function config_board_mux() reads env variable 'hwconfig' which is
only available after relocation for QSPI boot. Move calling
config_board_mux() to misc_init_r().
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
[YS: Revise commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Smart voltage translator is removed from LS2080ARDB/LS2088ARDB
RevF boards. It is only used on LS2081ARDB. Programming GPIO
is only required for LS2081ARDB.
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: NYork Sun <york.sun@nxp.com>

The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Add missing probe function to the device driver to active a device.
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

This defconfig uses the PCIe x4 binary blobs from the congatec BIOS.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

- Disable debug UART
- Enable more partition support
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

- Enable ACPI resume support
- Disable debug UART
- Enable Spansion and Winbond SPI flash support
- Move VGA BIOS binary address to enable bigger U-Boot images
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds the common header include file theadorable-x86-common.h
for the theadorable-x86 targets to define all common options and the
default environment.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds the infrastructure to define different config headers
with different configurations and default environment for the baseboards
that can now be selected via Kconfig. The new configuration for the
theadorable-x86-conga-qa3-e3845 is also added. Also the new defconfig
file for this new target is added.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>