- Move to gcc-11.1.0 builds from kernel.org for supported platforms and
  LLVM-11 for those tests.
- As Heinrich has noted, the RISC-V platform specification has a profile
  OS-A for running rich operating systems like Linux and BSD. This profile
  requires 64bit and UEFI conforming to the EBBR. Only the 'embedded'
  profile may use 32bit.  Given this, drop grub for 32bit RISC-V as it no
  longer compiles with gcc-11.1 and upstream is unlikely to fix it:
  https://www.mail-archive.com/grub-devel@gnu.org/msg30736.html
- Update to grub-2.06 release to address other issues of building with
  gcc-11.1.
- Update to newer Xtensa (gcc-9.2.0) and ARC (gcc-10.2) toolchains

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.

At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.

With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.

Drop the emulator definition when CONFIG_BIOSEMU is used.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

When we do not have bootstage enabled, rather than include an empty
dummy function, we just don't reference it.  This saves us space in some
tight builds.  This also shows a few cases where show_boot_progress was
incorrectly guarded before.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

Follow what the Linux Kernel does here and disable the
'zero-length-bounds', 'array-bounds' and 'stringop-overflow' warnings
here.

This brings in commits 5c45de21a2223, 44720996e2d79 and 5a76021c2eff7
from the Linux Kernel.
Signed-off-by: NTom Rini <trini@konsulko.com>

With gcc-11 we get a multiple errors here as the declarations for
mscc_pinctrl_ops and mscc_gpio_ops are missing an extern.

CC: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

The board code here references the display_width / display_height
variables set in the video driver, declare these as externs as gcc-11
will notice and lead to a multiple definition error.
Signed-off-by: NTom Rini <trini@konsulko.com>

In some board cpld.h files the definition of the cpld_data struct
not-quite makes a typedef for cpld_data_t.  This problem is caught with
gcc-11 as a multiple definition error.  As there are no users of this
non-typedef, fix this by not declaring it one to begin with.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

With gcc-11 we see:
drivers/ddr/marvell/a38x/ddr3_debug.c:672:47: error: argument 2 of type 'u32[5]' {aka 'unsigned int[5]'} with mismatched bound [-Werror=array-parameter=]
  672 | int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
      |                                           ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h:10,
                 from drivers/ddr/marvell/a38x/ddr3_init.h:17,
                 from drivers/ddr/marvell/a38x/ddr3_debug.c:6:
drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h:116:47: note: previously declared as 'u32[]' {aka 'unsigned int[]'}

And similar warnings.  Correct these by updating the prototype.  Remove
the prototype for ddr3_tip_read_pup_value as it is unused.
Signed-off-by: NTom Rini <trini@konsulko.com>

- mpc8379erdb DM_USB, DM_PCI and DM_ETH support.
- Drop PCI support from the integrator family of boards
- Add synquacer support
- Assorted lpc32xx updates and improvements
- snapdragon (and related) fixes, Broadcom iproc update

At the moment, the U-Boot serial_msm driver does not initialize the
UART_DM_DMEN register with the required value. Usually this does not
cause any problems, because there is Qualcomm's LK bootloader running
before U-Boot which initializes the register with the correct value.

It's important that this register is initialized correctly, because
the U-Boot driver does not make use of the BAM/DMA or single character
mode functionality of the UART controller. A different bootloader
before U-Boot might initialize the register differently.

For example, on DragonBoard 410c U-Boot can also be installed to the
"aboot" partition (replacing LK entirely). In this case U-Boot is
loaded directly by SBL, which seems to use the single-character mode
for some reason. In single character mode there is always just one
char in the FIFO, instead of the 4 characters expected by
msm_serial_fetch(). It also causes issues with "earlycon" later in
the Linux kernel, which tries to output 4 chars at once,
but only the first char will be written.

This causes early UART log in Linux to be corrupted like this:

    [ 00ano:ameoi .Q1B[ 00ac _idaM00080oo'ahani-lcle._20). 15NdNii 5 SPMSJ20:U2
    [ 00rkoolmsamel
    [ 00Fw ]elamletopsioble
    [ 00ore

instead of

    [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd030]
    [    0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC
    [    0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000078b0000 (options '')
    [    0.000000] printk: bootconsole [msm_serial_dm0] enabled

Make sure to initialize UART_DM_DMEN correctly to fix this issue
when loading U-Boot directly after SBL (instead of through LK).

There is no functional difference when loading U-Boot through LK
since LK also initializes UART_DM_DMEN to 0x0. [1]

[1]: https://git.linaro.org/landing-teams/working/qualcomm/lk.git/tree/platform/msm_shared/uart_dm.c?h=dragonboard410c-LA.BR.1.2.7-03810-8x16.0-linaro3#n203

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: NStephan Gerhold <stephan@gerhold.net>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

It looks like SD card detection is broken at the moment for DB410c.
The eMMC is detected correctly, but the SD card is not.

This is probably similar to the issue fixed in commit 85051474
("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC,
except that the SD card does not have a property like "non-removable"
that skips the card detection.

The SDHCI on DB410c cannot detect itself if a SD card is inserted,
so add the necessary cd-gpios to make SD card detection work again.

While at it, fix the #gpio-cells for the soc_gpios to avoid DTC
warnings - the soc_gpios are actually already used with two cells
for the gpio-leds so this was just wrong all the time.

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: NStephan Gerhold <stephan@gerhold.net>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

Fix typo in clock-snapdragon.c
Signed-off-by: NSheep Sun <sunxiaoyang2003@gmail.com>

The GICC register used by u-boot is 0x0a20c000, which is actually a GICC
for WCNSS, the WLAN processor. U-boot runs on the Application Processor,
therefore it should use APCS GICC instead. Hence, correct it with APCS GICC
register address.
Signed-off-by: NSheep Sun <sunxiaoyang2003@gmail.com>

Enable a DMed i2c driver for the ea-lpc3250devkitv2 board.
Include some sample commands/output for testing.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

Convert the CONFIG_SYS_I2C_LPC32XX configuration symbol from an include
directive to a Kconfig value.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add the of_match/compatible string to the lpc32xx i2c driver so it works
correctly with device-tree.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

The lpc32xx driver was not obtaining the per-device base address correctly
from the device tree. Fix the FIXME in order to get the correct base address.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

The LPC32XX_I2C_STAT_DRMI is not used anywhere so remove it.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

Add basic support for running U-Boot on the Embedded Artists LPC3250
Developer's Kit v2 board by launching U-Boot from the board's s1l loader
(which comes pre-installed on the board).
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board
directly and unmodified from the latest Linux kernel.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>

There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.
Signed-off-by: NTrevor Woerner <twoerner@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable EFI capsule update support. With the EFI capsule update,
you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are
usually combined as a FIP binary, but if the binary is bigger
than 480KB, you have to modify FIP header, split the OP-TEE
and stores the OP-TEE binary in the different place. This
configuration supports both cases.
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Since the EDK2 GenerateCapsule script is out of date and it
doesn't generate the supported version capsule file, the document
should refer the mkeficapsule in tools.
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.

For more information, see this page;
  https://www.96boards.org/product/developerbox/Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2

commit 83d38b0b4c0f240d4488c600bbe87cea391f3922

as-is (except for the changes #include path and some macros).

And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Add driver for class of I2C controllers found on
Socionext Synquacer platform.
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Add ECAM based SynQuacer PCIe RC driver. This driver configures the
PCIe RC and filter out a ghost pcie config.

Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device
is configured by firmware (EDK2), it doesn't re-configure in the kernel.
So as same as EDK2, U-Boot needs to configure it before boot the kernel.
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Since some SoCs and boards do not hae extra asm/arch/gpio.h,
introduce CONFIG_GPIO_EXTRA_HEADER instead of adding
!define(CONFIG_ARCH_XXXX) in asm/gpio.h.
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>

Commit bbbcb526 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.

Without this fix, "pci enum" command cause a synchronous abort.

pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [78000000-7fffffff],
		Physical Memory [78000000-7fffffffx]
PCI Autoconfig: Bus I/O region: [0-ffff],
		Physical Memory [77f00000-77f0ffffx]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000

PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000
PCI: Failed autoconfig bar 14

PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004

PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000

PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100

PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000

"Synchronous Abort" handler, esr 0x96000006
elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc)
elr: 00000000fff6fd28 lr : 00000000fff6fce8
x0 : 0000000000001041 x1 : 000000000000003e
x2 : 00000000ffb0f8c8 x3 : 0000000000000001
x4 : 0000000000000080 x5 : 0000000000000000
x6 : 00000000fff718fc x7 : 000000000000000f
x8 : 00000000ffb0f238 x9 : 0000000000000008
x10: 0000000000000000 x11: 0000000000000010
x12: 0000000000000006 x13: 000000000001869f
x14: 00000000ffb0fcd0 x15: 0000000000000020
x16: 00000000fff71cc4 x17: 0000000000000000
x18: 00000000ffb13d90 x19: 00000000ffb14320
x20: 0000000000000000 x21: 00000000ffb14090
x22: 00000000ffb0f8c8 x23: 0000000000000001
x24: 00000000ffb14c10 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000ffb14c70 x29: 00000000ffb0f830

Code: 52800843 52800061 52800e00 97ffcf65 (b9400280)
Resetting CPU ...
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: NMasami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
equivalent code in Broadcom's LDK 5.0.6.
Signed-off-by: NChris Packham <judge.packham@gmail.com>

We didn't convert the Integrator to use DM for PCI in
time, and we don't use it either so let's just drop
PCI support from the Integrator.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NSinan Akman <sinan@writeme.com>

There are two revisions of unmatched board with different DDR timing,
we'd like to support multi-dtb mechanism in SPL, then it selects the
right DTB at runtime according to PCB revision in I2C EEPROM.
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NLeo Yu-Chi Liang <ycliang@andestech.com>

The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NLeo Yu-Chi Liang <ycliang@andestech.com>

There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.
Signed-off-by: NZong Li <zong.li@sifive.com>
Reviewed-by: NLeo Yu-Chi Liang <ycliang@andestech.com>