- 07 9月, 2013 3 次提交
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由 Rob Herring 提交于
This fixes a memory leak when scsi inquiry fails. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Rob Herring 提交于
gcc 4.7 will generate unaligned accesses to local char arrays, so make them static to avoid that. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Richard Gibbs 提交于
The AHCI driver was incorrectly using the Capabilities register NP (number of ports) field to determine which ports to activate. This commit changes it to correctly use the PORTS_IMPL register as a port map. Signed-off-by: NRichard Gibbs <richard.gibbs@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 02 4月, 2013 1 次提交
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由 York Sun 提交于
'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 03 11月, 2012 15 次提交
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由 Walter Murphy 提交于
Currently, this driver uses a 28bit interface to AHCI, this limits the number of blocks addressable to 2^28, or the max disk size to 512(2^28) or about 137GB. This change allows supporting drives up to about 2TB. Testing this is a bit difficult. There is test code that can be inserted into U-Boot that will write test patterns into certain unused blocks. These patterns can be manually checked using 'dd' after boot. Another way is to confirm the original error that exposed this bug is fixed. IOW: see if AU (Auto Update) will now work on the drive. Also, check that there are no warning messages from the 'cgpt' utility. Signed-off-by: NWalter Murphy <wmurphy@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Marc Jones 提交于
Writes in u-boot are so rare, and the logic to know when is the last write and do a flush only there is sufficiently difficult. Just do a flush after every write. This incurs, usually, one extra flush when the rare writes do happen. Signed-off-by: NMarc Jones <marc.jones@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Marc Jones 提交于
Add HDD handling to the SSD-only AHCI driver, by separately dealing with spin-up and link-up. Signed-off-by: NMarc Jones <marc.jones@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Walter Murphy 提交于
Note: These are timeout values and not delay values, so the event being timed out will complete whenever it is actually ready, with a measurement granularity of 1 millisecond, up till the timeout value. Therefore, there is no effect on SSD booting. The values were determined by instrumenting the code and measuring the actual time taken by several different models of HDD for each of the parameters and then adding 50% more for the spinup value and just doubling the command timeout value. Signed-off-by: NWalter Murphy <wmurphy@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Taylor Hutt 提交于
Exynos5 automatically performs DMA when the SATA controller executes commands. This adds the necessary dcache-to-memory flush & invalidation calls to allow the DMA to properly function. Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Taylor Hutt 提交于
Update the assignment of various physical memory buffers used by the SATA controller to explicitly be denoted as physical addresses. The memory is identity-mapped, so these function calls are a nop, but they provide good semantic documentation for any maintainers. The return value of virt_to_phys() is 'unsigned long'. On machines where sizeof(unsigned long) != sizeof(pointer), a cast through (uintptr_t) is needed to appease the compiler due to the potential of losing the upper 32 bits of the address. In compilation this scenario, a physical address could be 64-bits, yet the C pointer environment only allows 32-bit addresses; the constraint is that pointers cannot address more than 4Gb of memory and if virt_to_phys() ever returns an out-of-range value for the physical address, there are issues with emmory mapping which must be solved. However, since the memory is identify mappeed, there is no problem introducing the cast: the original pointer will reside in 32-bits, so the physical address will also be within in 32-bits. Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Taylor Hutt 提交于
This fixes a spelling error in a message which can be output to the console. Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Taylor Hutt 提交于
This cleanup replaces the hardcoded use of '20', which represents the number of bytes in the FIS, with sizeof(fis). Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
In the structure returned by the ATA identify device command, there are two fields which describe the device capacity. One is a 32 bit data type which reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs, the small value is the only value with the correct size. If it supports more, if the number of sectors is small enough to fit into 28 bits, both fields reflect the correct value. If it's too large, the smaller field has 28 bits of 1s, 0xfffffff, and the other field has the correct value. The AHCI driver is implemented by attaching to the generic SCSI code and translating on the fly between SCSI binary data structures and AHCI data structures. It responds to requests to execute specific SCSI commands by executing the equivalent AHCI commands and then crafting a response which matches what a SCSI disk would send. The AHCI driver now considers both fields and chooses the correct one when implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Hung-Te Lin 提交于
The "scsi write" command requires support from underlying driver. This CL enables SCSI_WRITE10 in AHCI driver. Tested in U-Boot console, try to i/o with sector #64: scsi read 1000 40 1 md.b 1000 200 # check if things are not 0xcc mw.b 1000 cc 200 # try to fill with 0xcc scsi write 1000 40 1 mw.b 1000 0 200 # fill with zero md.b 1000 200 # should be all 0 scsi read 1000 40 1 md.b 1000 200 # should be all 0xcc Signed-off-by: NHung-Te Lin <hungte@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
This command doesn't really do anything when talking to a SATA device, and sending it confuses some of them. This change makes sending the command optional, and defaults to not. The situations where it should be sent are not the common case. With the standard SSD in the machine, here are some times with the option turned off: 1. 8277 2. 8273 3. 8050 And turned on: 1. 8303 2. 8155 3. 8276 Sending that command seems to have no meaningful effect on performance. This fixes problems with an SSD marked Toshiba NV6424, Taiwan 11159AE P and TC58NVG5D2FTA10. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Stefan Reinauer 提交于
- print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments For example, this might show the following string: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NStefan Reinauer <reinauer@chromium.org>
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由 Stefan Reinauer 提交于
- remove unused ssleep macro - add some useful debugging information Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Stefan Reinauer 提交于
The existing code waits a whole second for the AHCI controller to reset. Instead, let's poll the status register to see if the reset has succeeded and return earlier if possible. This brings down the time for AHCI probing from 1s to 20ms. Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Vadim Bendebury 提交于
With an Intel AHCI controller, the driver does not operate properly if the requested amount of blocks to read exceeds 255. It is probably possible to specify 0 as the block count and the driver will read 256 blocks, but it was decided to limit the number of blocks read at once to 128 (it should be a power of 2 for the optimal performance of solid state drives). Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 17 11月, 2011 1 次提交
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由 Kumar Gala 提交于
Fix: ahci.c: In function 'ata_scsiop_read10': ahci.c:564:6: warning: variable 'lba' set but not used [-Wunused-but-set-variable] Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 28 10月, 2011 1 次提交
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由 Marek Vasut 提交于
ahci.c: In function 'ahci_port_start': ahci.c:401: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'struct ahci_cmd_hdr *' Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
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- 26 7月, 2011 2 次提交
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由 Rob Herring 提交于
Add support for AHCI controllers that are not PCI based. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Wolfgang Denk <wd@denx.de>
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由 Rob Herring 提交于
The ata id string always needs swapping, not just on BE machines. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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- 29 7月, 2009 1 次提交
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由 Kumar Gala 提交于
"All Rights Reserved" conflicts with the GPL. Signed-off-by: NKumar Gala <kumar.gala@freescale.com>
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- 24 7月, 2009 1 次提交
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由 Kumar Gala 提交于
ahci.c: In function 'ata_scsiop_read_capacity10': ahci.c:616: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 2月, 2009 1 次提交
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由 Becky Bruce 提交于
The code assumes that the pci bus address and the virtual address used to access a region are the same, but they might not be. Fix this assumption. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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- 19 10月, 2008 1 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 13 8月, 2008 1 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 26 11月, 2007 1 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 15 8月, 2007 1 次提交
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由 Ed Swarthout 提交于
Typically this causes scsi init to corrupt the devlist and break the coninfo command. Fix a compiler size warning. Signed-off-by: NJason Jin <jason.jin@freescale.com> Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com>
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- 06 8月, 2007 1 次提交
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由 Ed Swarthout 提交于
All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NZhang Wei <wei.zhang@freescale.com> Signed-off-by: NJon Loeliger <jdl@freescale.com>
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- 24 8月, 2006 1 次提交
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由 Jon Loeliger 提交于
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- 23 8月, 2006 1 次提交
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由 Jin Zhengxiong 提交于
Add AHCI support in u-boot, enable the sata disk controllers which following the AHCI protocol. Signed-off-by:Jason Jin<jason.jin@freescale.com>
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