- 25 11月, 2020 1 次提交
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由 Patrick Delaunay 提交于
Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour call: the address must use ALIGN_DOWN and size can use ALIGN macro. With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for STM32MP15x the computed address was 30000000 instead of 2ff00000. Fixes: 43fe9d2f ("stm32mp1: mmu_set_region_dcache_behaviour") Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 22 10月, 2020 1 次提交
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由 Patrick Delaunay 提交于
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 09 9月, 2020 1 次提交
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由 Patrick Delaunay 提交于
Remove the unnecessary inversion on the eth_env_set_enetaddr() result which only make complex the code of setup_mac_address() and display an invalid value in the associated pr_err. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NMarek Vasut <marex@denx.de>
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- 28 7月, 2020 2 次提交
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由 Patrick Delaunay 提交于
Since commit d877f8fd ("arm: provide a function for boards init code to modify MMU virtual-physical map") the parameter of mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE aligned. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
As the dbgmcu_init use the function bsec_dbgswenable which is based on the DM and DT, its call can't be done before the spl is initialized (driver model, DT and malloc) in board_init_f::spl_early_init(). This function call is moved later in spl_board_init(). Fixes: bd3f60d2 ("arm: stm32mp: protect DBGMCU_IDC access with BSEC") Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 07 7月, 2020 1 次提交
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由 Patrick Delaunay 提交于
As debugger must be totally closed on Sec closed chip, the DBGMCU_IDC register is no more accessible (self hosted debug is disabled with OTP). This patch adds a function bsec_dbgswenable() to check if the DBGMCU registers are available before to access them: BSEC_DENABLE.DBGSWENABLE = self hosted debug status. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 19 5月, 2020 4 次提交
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由 Simon Glass 提交于
Move this uncommon header out of the common header. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this header out of the common header. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this uncommon header out of the common header. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 14 5月, 2020 3 次提交
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由 Patrick Delaunay 提交于
Activate the data cache in SPL and in U-Boot before relocation. In arch_cpu_init(), the function early_enable_caches() sets the early TLB, early_tlb[] located .init section, and set cacheable: - for SPL, all the SYSRAM - for U-Boot, all the DDR After relocation, the function enable_caches() (called by board_r) reconfigures the MMU with new TLB location (reserved in board_f.c::reserve_mmu) and re-enable the data cache. This patch allows to reduce the execution time, particularly - for the device tree parsing in U-Boot pre-reloc stage (dm_extended_scan_fd =>dm_scan_fdt) - in I2C timing computation in SPL (stm32_i2c_choose_solution()) For example, the result on STM32MP157C-DK2 board is: 1,6s gain for trusted boot chain with TF-A 2,2s gain for basic boot chain with SPL For information, as TLB is added in .data section, the binary size increased and the SPL load time by ROM code increased (30ms on DK2). But early malloc can't be used for TLB because arch_cpu_init() is executed before the early poll initialization done in spl_common_init() called by spl_early_init() So it too late for this use case. And if I initialize the MMU and the cache after this function it is too late, as dm_init_and_scan and fdt parsing is also called in spl_common_init(). And .BSS can be used in board_init_f(): only stack and global can use before BSS init done in board_init_r(). So .data is the better solution without hardcoded location but if you have size issue for SPL you can deactivate cache for SPL only (with CONFIG_SPL_SYS_DCACHE_OFF). Reviewed-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Add a function get_cpu_dev to get the DEV_ID present in DBGMCU_IDC register. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Manage BOOT_FLASH_SPINAND, with boot_device="spi-nand" and treat this value in bootcmd_stm32mp. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 15 4月, 2020 1 次提交
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由 Patrick Delaunay 提交于
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a1 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 24 3月, 2020 3 次提交
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由 Patrick Delaunay 提交于
The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add a function get_soc_name to get a string with the full name of the SOC "STM32MP15xxx Rev.x" Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver. The write access only available for Trusted boot mode, based on new SMC STM32_SMC_WRLOCK_OTP. With the fuse command, the permanent lock status is accessed with 0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program divided by u32 size), for example: Read lock status of fuse 57 (0x39) STM32MP> fuse sense 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 Set permanent lock of fuse 57 (0x39) STM32MP> fuse prog 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 WARNING: the OTP lock is updated only after reboot WARING: Programming lock or fuses is an irreversible operation! This may brick your system. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com>
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- 14 2月, 2020 1 次提交
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由 Patrick Delaunay 提交于
Add support for Rev.Z of STM32MP15x cpu. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 17 1月, 2020 1 次提交
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由 Marek Vasut 提交于
Let board code override setup_mac_address(), which is useful e.g. if the board derives the MAC address from another source, like an I2C EEPROM. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 08 1月, 2020 1 次提交
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由 Fabien Dessenne 提交于
Reset ResourceTableAddress and CoprocessorState at cold boot, preserve these values at standby wakeup. Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com> Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 03 12月, 2019 1 次提交
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由 Simon Glass 提交于
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 12 8月, 2019 2 次提交
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由 Simon Glass 提交于
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move env_set() over to the new header file. Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 12 7月, 2019 2 次提交
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由 Patrick Delaunay 提交于
This patch solves the following warnings: arch/arm/mach-stm32mp/cpu.c:378:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] if (instance > ARRAY_SIZE(serial_addr)) ^ Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Prepare update of package information update in Linux device tree. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 06 6月, 2019 1 次提交
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由 Manivannan Sadhasivam 提交于
Without newline, the error message appears for non prgrammed OTP boards looks messsy. Hence add it to look more clean. Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 12 4月, 2019 7 次提交
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由 Patrick Delaunay 提交于
Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to increase read performance. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank (open security). Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Always use upper case for serial number. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
The boot mode can be forced by key press or by TAMP register, requested in kernel by syscon-reboot-mode tamp: tamp@5c00a000 { compatible = "simple-bus", "syscon", "simple-mfd"; reg = <0x5c00a000 0x400>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x150>; /* reg20 */ mask = <0xff>; mode-normal = <0>; mode-fastboot = <0x1>; mode-recovery = <0x2>; mode-stm32cubeprogrammer = <0x3>; mode-ums_mmc0 = <0x10>; mode-ums_mmc1 = <0x11>; mode-ums_mmc2 = <0x12>; }; }; Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Display CPU part number and package information. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
- export the function get_bootmode() and reused it in spl code - manage uart instance by alias (prepare v4.19 binding) - solve issue on nand instance - restore console for uart boot Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 21 11月, 2018 1 次提交
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由 Simon Glass 提交于
At present these functions return 0 on success. For some devices we want to know how many bytes were transferred. It seems useful to adjust the API to be more like the POSIX read() and write() functions. Update these two methods, a test and all users. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 27 5月, 2018 2 次提交
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由 Patrick Delaunay 提交于
Use OTP57 and 58 for MAC address - OTP57 = MAC address bits [31:0] - OTP58 = MAC address bit [47:32] stored in OTP LSB's Use manufacture information in OTP13 to OTP15 to build unique chip id saved in env variable "serial#" (used for USB device enumeration) Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add the needed information to enable the debug uart to have printf before the serial driver probe (so before probe for clock, pincontrol and reset drivers) To enable the debug on uart 4 (default console): + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_STM32=y Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
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- 07 5月, 2018 1 次提交
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由 Tom Rini 提交于
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NTom Rini <trini@konsulko.com>
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- 07 4月, 2018 3 次提交
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由 Patrick Delaunay 提交于
Add support of sysreset with generic driver "syscon-reboot" provided by RCC, for U-boot and for SPL. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
SPL copy BootRom boot mode information in TAMP register 21. This TAMP register information is used after relocation to set 2 env variables - boot_device - boot_instance Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
Add support of DBGMCU_IDC for cpu identifier and revision Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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