Signed-off-by: NTim Harvey <tharvey@gateworks.com>

There is no ethaddr assigned to each board, so we need to use random
value in order to use network.
Signed-off-by: NMarcin Niestroj <m.niestroj@grinn-global.com>

This patch mostly enables DM drivers in board defconfig and all their
dependencies. Additionally we remove USB code that is on longer
executed after enabling CONFIG_DM_USB. Enable CONFIG_PINCTRL, so we
can get rid of ethernet pin configuration.
Signed-off-by: NMarcin Niestroj <m.niestroj@grinn-global.com>

After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Convert to use DM_PMIC for the PFUZE3000. Since this PMIC is
under an I2C bus, conver to DM_I2C as well.

Also, since I2C is not used in SPL, remove CONFIG_SPL_I2C_SUPPORT
to avoid build warnings.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Convert to CONFIG_DM_GPIO.

Also, DM GPIO requires gpio_request() to be called explicitly before
doing any gpio operation, so do as requested.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Select CONFIG_DM_MMC=y in order to support MMC driver model.

This allows the MMC board related code to be removed.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Select CONFIG_OF_CONTROL and the appropriate device tree files
in preparation for converting to driver model.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

The Ethernet controller is not able to initialise correctly without the
pinctrl driver.

This config setting was enabled in the initial version of this file,
but was removed by a savedefconfig resync because the parameter did not
actually exist at that point.

Fixes: 1bac199e ("configs: Resync with savedefconfig")
Signed-off-by: NChris Spencer <christopher.spencer@sea.co.uk>
Reviewed-by: NFabio Estevam <festevam@gmail.com>

Add i.mx8m pinctrl driver.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

- axp818 fix
- fix warnings for ethernet clock code

- ACPI changes and fixes to Intel Tangier/Edison
- i8254 beeper fixes

Use the i8254 sound driver to support creating simple beeps.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is currently missing and without it the i8254 beeper driver
won't work.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- Arria10 DRAM fixes and Gen5 cache fixes

- More gen2/gen3 fixes

Intel Edison has three UART ports, i.e.
 port 0 - Bluetooth
 port 1 - auxiliary, available for general purpose use
 port 2 - debugging, usually console output is here

Enable all of them for future use.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.

Thus, fix the number of default console interface to be 2.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad7 ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.

This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
checking for specific board configuration, which works with one
single platform in tree, but not with multiple. Fix it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

This is not used anywhere, so drop it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The debug print is missing a newline, add it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

v2019.01 commit cbff9f80 ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.

Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
 - f529bc55 ("ARM: dts: rmobile: Extract USB nodes on M3N")
 - 830b94f7 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")

Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
 - not needed if no U-boot-specific changes are needed in those nodes.
 - potentially dangerous/error-prone, since the duplicated properties
   override the properties originally defined in <soc>.dtsi. One
   possible consequence is that <soc>.dtsi is getting an update from
   Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
   the obsolete property values from <soc>-u-boot.dtsi will take
   precedence masking some of the <soc>.dtsi updates, potentially
   leading to all kind of obscure issues.

Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).

What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.

$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
           after-r8a77965-salvator-x-u-boot.dtb
 --- /dev/fd/63  2019-03-09 12:57:40.877963983 +0100
 +++ /dev/fd/62  2019-03-09 12:57:40.877963983 +0100
 @@ -1471,7 +1471,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x51 0xc 0x1>;
        clocks = <0x6 0x1 0x13a>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa5 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x4d>;
 @@ -1492,7 +1492,7 @@

      sd@ee120000 {
        clocks = <0x6 0x1 0x139>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa6 0x4>;
        max-frequency = <0xbebc200>;
        power-domains = <0x1 0x20>;
 @@ -1504,7 +1504,7 @@
      sd@ee140000 {
        bus-width = <0x8>;
        clocks = <0x6 0x1 0x138>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        fixed-emmc-driver-type = <0x1>;
        interrupts = <0x0 0xa7 0x4>;
        max-frequency = <0xbebc200>;
 @@ -1526,7 +1526,7 @@
        bus-width = <0x4>;
        cd-gpios = <0x5a 0xf 0x1>;
        clocks = <0x6 0x1 0x137>;
 -      compatible = "renesas,sdhi-r8a77965";
 +      compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
        interrupts = <0x0 0xa8 0x4>;
        max-frequency = <0xc65d400>;
        pinctrl-0 = <0x56>;
 @@ -1868,14 +1868,14 @@

      usb-phy@ee0a0200 {
        #phy-cells = <0x0>;
 -      clocks = <0x6 0x1 0x2be>;
 +      clocks = <0x6 0x1 0x2bf>;
        compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
        phandle = <0x47>;
        pinctrl-0 = <0x4c>;
        pinctrl-names = "default";
        power-domains = <0x1 0x20>;
        reg = <0x0 0xee0a0200 0x0 0x700>;
 -      resets = <0x6 0x2be>;
 +      resets = <0x6 0x2bf>;
        status = "okay";
      };
Signed-off-by: NEugeniu Rosca <erosca@de.adit-jv.com>

v2019.01 commit 07a8060a ("ARM: rmobile: Convert to bootm_size")
attempted converting to bootm_size of 256 MiB below targets:
 - include/configs/alt.h
 - include/configs/gose.h
 - include/configs/koelsch.h
 - include/configs/lager.h
 - include/configs/porter.h
 - include/configs/rcar-gen3-common.h
 - include/configs/silk.h
 - include/configs/stout.h

The update didn't fully work on R-Car3 due to the
CONFIG_SYS_BOOTMAPSZ=8MiB definition left by v2016.09 commit
e525d34b ("ARM: rmobile: Add support salvator-x board"),
which is explained in below README excerpt:

----8<----
CONFIG_SYS_BOOTMAPSZ:
                [..] If CONFIG_SYS_BOOTMAPSZ is undefined,
                then the value in "bootm_size" will be used instead.
----8<----

Allow the original commit to accomplish its purpose on R-Car3 targets
by removing the CONFIG_SYS_BOOTMAPSZ definition.

Fixes: 07a8060a ("ARM: rmobile: Convert to bootm_size")
Signed-off-by: NEugeniu Rosca <erosca@de.adit-jv.com>

Enable DM_SPI and DM_SPI_FLASH in U-Boot on H2 Stout, M2W Porter and E3 Silk.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

- Implement EMAC, GMAC clocks via ccu_clk_gate for
  all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
  supported Allwinner SoCs.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>