- 15 5月, 2012 32 次提交
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由 Aneesh V 提交于
Use ENTRY and ENDPROC with assembly functions to ensure necessary assembler directives for all functions. Signed-off-by: NAneesh V <aneesh@ti.com> Acked-by: NMike Frysinger <vapier@gentoo.org>
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由 Aneesh V 提交于
This will add ARM specific over-rides for the defines from linux/linkage.h Signed-off-by: NAneesh V <aneesh@ti.com> Tested-by: NMike Frysinger <vapier@gentoo.org>
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由 SRICHARAN R 提交于
Warm reset is not functional in case of omap5430ES1.0. So override the weak reset_cpu function to use cold reset instead. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The reset.S has the function to do a warm reset on OMAP based socs. Moving this to a reset.c file so that this acts a common layer to add any reset related functionality for the future. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 Balaji T K 提交于
Save env to eMMC Signed-off-by: NBalaji T K <balajitk@ti.com>
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由 Balaji T K 提交于
Add omap5 pbias configuration for mmc1/sd lines and set voltage for sd data i/o lines Signed-off-by: NBalaji T K <balajitk@ti.com>
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由 SRICHARAN R 提交于
palmas/TWL6035 is power IC for omap5 evm boards Signed-off-by: NBalaji T K <balajitk@ti.com>
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由 Balaji T K 提交于
In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC Signed-off-by: NBalaji T K <balajitk@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 SRICHARAN R 提交于
PD_TIM bit field which specifies the power down timing is defined to occupy bits 8-11, where as it is actually from 12-15 bits. So correcting this. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and not a ELPIDA part. So change this. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
Adding the nessecary changes for OMAP5430 ES1.0 silicon. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
Add support to identify the device as GP/EMU/HS. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
Make the sysctrl structure common, so that it can be used in generic functions across socs. Also change the base address of the system control module, to include all the registers and not simply the io regs. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The full internal SRAM of size 128kb is public in the case of OMAP5 soc. So change the base address accordingly. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The break statement is missing in init_omap_revision function, resulting in a wrong revision identification. So fixing this. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.htmlSigned-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
The control module provides options to set various signal integrity parameters like the output impedance, slew rate, load capacitance for different pad groups. Configure these as required for the omap5430 sevm board. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
Adding the full pinmux data for OMAP5430 sevm board. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 SRICHARAN R 提交于
Aligning all the clock related settings like the dpll frequencies, their respective clock outputs, etc to the ideal values recommended for OMAP5430 ES1.0 silicon. Signed-off-by: NR Sricharan <r.sricharan@ti.com>
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由 Enric Balletbò i Serra 提交于
This is rework on config files of IGEP-based boards with the aim to remove duplicated code to be more maintainable. Basically this patch creates a common configuration file for both boards and only sets the specific option in the board config file. On board files the hardcored mach type was replaced in favour of using the CONFIG_MACH_TYPE option. More than 200 duplicated lines have been deleted. Signed-off-by: NEnric Balletbo i Serra <eballetbo@gmail.com>
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由 Nishanth Menon 提交于
OMAP4 requires that parent domains scale ahead of dependent domains. This is due to the restrictions in timing closure. To ensure a consistent behavior across all OMAP4 SoC, ensure that vdd_core scale first, then vdd_mpu and finally vdd_iva. As part of doing this refactor the logic to allow for future addition of OMAP4470 without much ado. OMAP4470 uses different SMPS addresses and cannot be introduced in the current code without major rewrite. Reported-by: NIsabelle Gros <i-gros@ti.com> Reported-by: NJerome Angeloni <j-angeloni@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: NIsabelle Gros <i-gros@ti.com> Reported-by: NJerome Angeloni <j-angeloni@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: NIsabelle Gros <i-gros@ti.com> Reported-by: NJerome Angeloni <j-angeloni@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Jonathan Solnit 提交于
Add parameters to the OMAP MMC initialization function so the board can mask host capabilities and set the maximum clock frequency. While the OMAP supports a certain set of MMC host capabilities, individual boards may be more restricted and the OMAP may need to be configured to match the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example. Signed-off-by: NJonathan Solnit <jsolnit@gmail.com>
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由 David Purdy 提交于
This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgraySigned-off-by: NDave Purdy <david.c.purdy@gmail.com> Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net
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由 Luka Perkov 提交于
Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515Signed-off-by: NLuka Perkov <uboot@lukaperkov.net> Signed-off-by: NGerald Kerma <dreagle@doukki.net> Signed-off-by: NSimon Baatz <gmbnomis@gmail.com>
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由 Vladimir Zapolskiy 提交于
This change adds a basic support for Embest/Timll DevKit3250 board, NOR and UART are the only supported peripherals for a moment. The board doesn't require low-level init, because the initial SDRAM and GPIO configuration is performed during kickstart bootloader execution. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Vladimir Zapolskiy 提交于
This change adds an implementation of high-speed UART found on NXP LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Vladimir Zapolskiy 提交于
This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Ian Campbell 提交于
I have tested booting both FDT and non-FDT based Linux kernels (based on http://marc.info/?l=linux-arm-kernel&m=133002679716986 and http://marc.info/?l=linux-arm-kernel&m=132328894303581 respectively). Signed-off-by: NIan Campbell <ijc@hellion.org.uk> Cc: Jason <jason@lakedaemon.net> Cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: NJason Cooper <jason@lakedaemon.net>
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- 01 5月, 2012 1 次提交
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git://git.denx.de/u-boot-staging由 Wolfgang Denk 提交于
* 'agust@denx.de' of git://git.denx.de/u-boot-staging: lin_gadget: use common linux/compat.h linux/compat.h: rename from linux/mtd/compat.h lin_gadget: use common mdelay gunzip: rename z{alloc, free} to gz{alloc, free} fs/fat: align disk buffers on cache line to enable DMA and cache part_dos: align disk buffers on cache line to enable DMA and cache
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- 30 4月, 2012 7 次提交
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由 Wolfgang Denk 提交于
* 'master' of /home/wd/git/u-boot/custodians: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
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git://git.denx.de/u-boot-ppc4xx由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-ppc4xx: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
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由 Mike Frysinger 提交于
Merge our duplicate definitions with the common header. Also fix drivers/usb/gadget/s3c_udc_otg_xfer_dma.c to use min() instead of min_t() since we remove the latter from compat.h. Additionally use memalign() directly as the lin_gadget specific kmalloc() macro is removed from lin_gadget_compat.h by this patch. Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NAnatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
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由 Mike Frysinger 提交于
This lets us use it in more places than just mtd code. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
No need to provide our own mdelay() macro when we have a func for it. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
This allows us to add a proper zalloc() func (one that does a zeroing alloc), and removes duplicate prototypes. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Acked-by: NMike Frysinger <vapier@gentoo.org>
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