- 18 7月, 2019 17 次提交
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由 AKASHI Takahiro 提交于
If U-Boot is loaded and started from TF-A (you need to change SYS_TEXT_BASE to 0x60000000), it will hang up at flash initialization. If secure mode is off (default, or -machine virt,secure=off) at qemu, it will provide dtb with two flash memory banks: flash@0 { bank-width = <0x4>; reg = <0x0 0x0 0x0 0x4000000 0x0 0x4000000 0x0 0x4000000>; compatible = "cfi-flash"; }; If secure mode is on, on the other hand, qemu provides dtb with 1 bank: flash@0 { bank-width = <0x4>; reg = <0x0 0x4000000 0x0 0x4000000>; compatible = "cfi-flash"; }; As a result, flash_init()/flash_get_size() will eventually fail. With this patch applied, relevant CONFIG values are modified. Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org> Tested-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 AKASHI Takahiro 提交于
Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig, but it will be also useful for other targets if some additional configuration are necessary. So move it to arch/arm/Kconfig. Please note that CONFIG_TFABOOT still depends on CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up if any target doesn't need its own customization for TF-A boot. This will maintain the compatibility. Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Sriram Dash <sriram.dash@nxp.com> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Peng Ma <peng.ma@nxp.com> Cc: Yuantian Tang <andy.tang@nxp.com> Cc: Pankit Garg <pankit.garg@nxp.com>
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由 Sam Protsenko 提交于
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>
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由 Jean-Jacques Hiblot 提交于
This command fills the memory with data produced by rand(). Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Andre Przywara 提交于
At the moment mkenvimage has two separate read paths: One to read from a potential pipe, while dynamically increasing the buffer size, and a second one using mmap(2), using the input file's size. This is problematic for two reasons: - The "pipe" path will be chosen if the input filename is missing or "-". Any named, but non-regular file will use the other path, which typically will cause mmap() to fail: $ mkenvimage -s 256 -o out <(echo "foo=bar") - There is no reason to have *two* ways of reading a file, since the "pipe way" will always work, even for regular files. Fix this (and simplify the code on the way) by always using the method of dynamically resizing the buffer. The existing distinction between the two cases will merely be used to use the open() syscall or not. Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
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由 Andre Przywara 提交于
It is perfectly fine for the read(2) syscall to return with less than the requested number of bytes read (short read, see the "RETURN VALUE" section of the man page). This typically happens with slow input (keyboard, network) or with complex pipes. So far mkenvimage expects the exact number of requested bytes to be read, assuming an end-of-file condition otherwise. This wrong behaviour can be easily shown with: $ (echo "foo=bar"; sleep 1; echo "bar=baz") | mkenvimage -s 256 -o out - The second line will be missing from the output. Correct this by checking for any positive, non-zero return value. This fixes a problem with a complex pipe in one of my scripts, where the environment consist of two parts. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NAlexander Dahl <ada@thorsis.com>
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由 Sam Protsenko 提交于
sgdisk 0.8.10.2 from AOSP doesn't support short options, failing with errors like this: sgdisk: invalid option -- 'U' Test fails due to that error. Let's use long options to make the test work with any sgdisk version. Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com>
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由 Frank Wunderlich 提交于
this adds erase environment for mmc storage squashed fixes: - add CONFIG_CMD_ERASEENV - env: erase redundant offset if defined - changes mentioned by Simon - fix whitespaces around errmsg Suggested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: NFrank Wunderlich <frank-w@public-files.de> Reviewed-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Frank Wunderlich 提交于
this patch adds basic changes for adding a erase-subcommand to env with this command the environment stored on non-volatile storage written by saveenv can be cleared. Signed-off-by: NFrank Wunderlich <frank-w@public-files.de> squashed fixes - start message with "Erasing" - mark erase-function as optional - env: separate eraseenv from saveenv Suggested-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Marek Vasut 提交于
The autocompletion did not work if CONFIG_CMDLINE_PS_SUPPORT was enabled because U-Boot was comparing the prompt string with CONFIG_SYS_PROMPT . While this works if CONFIG_CMDLINE_PS_SUPPORT is disabled, this no longer works if it's enabled because user can override the PS1 . Fix this by checking prompt string against the current PS1 value. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
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由 Sven Schwermer 提交于
Drivers need to be able to enable regulators that may be implemented as GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is commonly implemented as a GPIO regulator in order to switch between I/O voltage levels. Signed-off-by: NSven Schwermer <sven@svenschwermer.de> Reviewed-by: NLukasz Majewski <lukma@denx.de>
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由 Sven Schwermer 提交于
In preparation of being able to enable/disable GPIO regulators, the code that will be shared among the two kinds to regulators is factored out into its own source files. Signed-off-by: NSven Schwermer <sven@svenschwermer.de> Reviewed-by: NLukasz Majewski <lukma@denx.de>
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由 Heinrich Schuchardt 提交于
When a crash occurs in thumb mode the crash dump is incorrect. This is due to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in the definition of macro thumb_mode(regs). Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt. With the patch crash dumps indicate thumb mode correctly. On a system with thumb mode: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 The Flags line has '(T)' and in the Code line the output is in u16 groups. On a system without thumb mode: => exception breakpoint prefetch abort pc : [<7ff5a5c8>] lr : [<7ff675ec>] reloc pc : [<0000e5c8>] lr : [<0001b5ec>] sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214 r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000 r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e) The Flags line does not show '(T)' and in the Code line the output is in u32 groups. Reported-by: NMarek Vasut <marex@denx.de> Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NMarek Vasut <marex@denx.de>
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由 Marek Szyprowski 提交于
JOURNAL is optional for EXT4 (and EXT3) filesystems, so add support for skipping it. This fixes corrupting EXT4 volumes without JOURNAL after using uboot's 'ext4write' command. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: NLukasz Majewski <lukma@denx.de>
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由 Marek Szyprowski 提交于
The block count entry in the EXT4 filesystem disk structures uses standard 512-bytes units for most of the typical files. The only exception are HUGE files, which use the filesystem block size, but those are not supported by uboot's EXT4 implementation anyway. This patch fixes the EXT4 code to use proper unit count for inode block count. This fixes errors reported by fsck.ext4 on disks with non-standard (i.e. 4KiB, in case of new flash drives) PHYSICAL block size after using 'ext4write' uboot's command. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: NLukasz Majewski <lukma@denx.de>
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由 Chuanhua Han 提交于
Add an implementation of the ds3231 driver that uses the driver model i2c APIs. Signed-off-by: NChuanhua Han <chuanhua.han@nxp.com> Reviewed-by: NLukasz Majewski <lukma@denx.de>
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由 Vesa Jääskeläinen 提交于
There are multiple other openssl engines used by HSMs that can be used to sign FIT images instead of forcing users to use pkcs11 type of service. Relax engine selection so that other openssl engines can be specified and use generic key id definition formula. Signed-off-by: NVesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Cc: Tom Rini <trini@konsulko.com>
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- 16 7月, 2019 23 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi由 Tom Rini 提交于
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
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由 Andre Przywara 提交于
So far USB was not enabled for the Allwinner H6 boards, as the PHY driver was not ready and the clock gates were missing. Since this is now fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for all existing H6 boards. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jernej Skrabec 提交于
Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: NJernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
The DRAM controller manual suggests to first program the PHY initialisation parameters to the PHY_PIR register, and then set bit 0 to trigger the initialisation. This is also used in boot0. Follow this recommendation by setting bit 0 in a separate step. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Andre Przywara 提交于
Using memcpy() is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Radu Pirea 提交于
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: NRadu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Radu Pirea 提交于
If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: NRadu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Grygorii Strashko 提交于
Enable TI K3 AM65x CPSW NUSS driver. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Grygorii Strashko 提交于
Add mcu cpsw nuss pinmux and phy defs required by cpsw. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Grygorii Strashko 提交于
Add mcu cpsw and its components along with scm_conf node to have ethernet functional. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Keerthy 提交于
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Keerthy 提交于
Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Yinbo Zhu 提交于
This patch is to use block layer to read from mmc in cortina Signed-off-by: NYinbo Zhu <yinbo.zhu@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Horatiu Vultur 提交于
Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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