- 13 3月, 2019 20 次提交
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由 Fabio Estevam 提交于
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NPeng Fan <peng.fan@nxp.com>
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由 Martyn Welch 提交于
The information in the SabreLite README is inaccurate and sparse. The upstream U-Boot can boot the SabreLite from SPI-NOR. Additionally, the freely available imx_loader tool can be easily used to boot a board with a corrupted SPI, the official Freescale/NXP manufacturing tools are not required. Reformat the document, adding a description of how to boot from SPI-NOR and adding a brief description of how to recover the board should the SPI-NOR be corrupted using imx_loader. Signed-off-by: NMartyn Welch <martyn.welch@collabora.com> Acked-by: NTroy Kisky <troy.kisky@boundarydevices.com>
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由 Baruch Siach 提交于
Remove a redundant directory level. Reported-by: NOfer Heifetz <ofer.heifetz@valens.com> Tested-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Baruch Siach 提交于
Tested-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Fabio Estevam 提交于
The third parameter of the pmic_clrsetbits() function is the mask to the register and the correct mask is 1 not 0. Since the LDOGCTL only contains a single valid bit (bit 0), we can use pmic_reg_write() and write 1 directly, which fixes the problem in a simpler way and use the original pmic function that was used prior to the DM PMIC conversion. Fixes: 8ba37732 ("arm: imx7s-warp: Convert to DM PMIC") Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Fabio Estevam 提交于
There is no need to store the values written to the PMIC inside the 'reg' variable. Make it simpler by writing the values directly. Signed-off-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Fabio Estevam 提交于
After DM conversion the I2C and MMC related board codes have been removed, so remove the corresponding header files as well. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Fabio Estevam 提交于
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Tim Harvey 提交于
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Marcin Niestroj 提交于
There is no ethaddr assigned to each board, so we need to use random value in order to use network. Signed-off-by: NMarcin Niestroj <m.niestroj@grinn-global.com>
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由 Marcin Niestroj 提交于
This patch mostly enables DM drivers in board defconfig and all their dependencies. Additionally we remove USB code that is on longer executed after enabling CONFIG_DM_USB. Enable CONFIG_PINCTRL, so we can get rid of ethernet pin configuration. Signed-off-by: NMarcin Niestroj <m.niestroj@grinn-global.com>
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由 Fabio Estevam 提交于
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
Convert to use DM_PMIC for the PFUZE3000. Since this PMIC is under an I2C bus, conver to DM_I2C as well. Also, since I2C is not used in SPL, remove CONFIG_SPL_I2C_SUPPORT to avoid build warnings. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
Convert to CONFIG_DM_GPIO. Also, DM GPIO requires gpio_request() to be called explicitly before doing any gpio operation, so do as requested. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
Select CONFIG_DM_MMC=y in order to support MMC driver model. This allows the MMC board related code to be removed. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
Select CONFIG_OF_CONTROL and the appropriate device tree files in preparation for converting to driver model. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
Import the device tree files from kernel 5.0-rc6 in preparation for driver model conversion. Signed-off-by: NFabio Estevam <festevam@gmail.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Chris Spencer 提交于
The Ethernet controller is not able to initialise correctly without the pinctrl driver. This config setting was enabled in the initial version of this file, but was removed by a savedefconfig resync because the parameter did not actually exist at that point. Fixes: 1bac199e ("configs: Resync with savedefconfig") Signed-off-by: NChris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: NFabio Estevam <festevam@gmail.com>
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由 Peng Fan 提交于
Add i.mx8m pinctrl driver. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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- 12 3月, 2019 1 次提交
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- 11 3月, 2019 5 次提交
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git://git.denx.de/u-boot-x86由 Tom Rini 提交于
- ACPI changes and fixes to Intel Tangier/Edison - i8254 beeper fixes
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由 Bin Meng 提交于
Use the i8254 sound driver to support creating simple beeps. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This is currently missing and without it the i8254 beeper driver won't work. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
The pc speaker driven by the i8254 is generic enough to deserve a single dtsi file to be included by boards that use it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
The i8254 timer control IO port (0x43) should be setup correctly by using PIT counter 2 to generate beeps, however in U-Boot other codes like TSC driver utilizes PIT for TSC frequency calibration and configures the counter 2 to a different mode that does not beep. Fix this by always ensuring the PIT counter 2 is correctly initialized so that the i8254 beeper driver works as expected. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 10 3月, 2019 14 次提交
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由 Andy Shevchenko 提交于
Intel Edison has three UART ports, i.e. port 0 - Bluetooth port 1 - auxiliary, available for general purpose use port 2 - debugging, usually console output is here Enable all of them for future use. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andy Shevchenko 提交于
The console is actually serial #2. When we would like to enable other ports, this would be not okay to mess up with the ordering. Thus, fix the number of default console interface to be 2. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andy Shevchenko 提交于
We may not do an assumption that current console device is always a first of UCLASS_SERIAL one. For example, on properly described Intel Edison board the console UART is a third one. Use current serial device as described in global data. Fixes: a61cbad7 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andy Shevchenko 提交于
Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andy Shevchenko 提交于
Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Marek Vasut 提交于
Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
The Kconfig checked for SoCFPGA Arria10 as a platform, instead of checking for specific board configuration, which works with one single platform in tree, but not with multiple. Fix it. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
This is not used anywhere, so drop it. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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由 Marek Vasut 提交于
The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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