Add xm011 DTS file and related configs and configurations.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Platform DTSes are missing content needed for platform to be able to use
OF binding and DM.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.
Signed-off-by: NEzra Savard <ezra.savard@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add pl310 interrupt to the Zynq devicetree.
Signed-off-by: NAlex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Trivial.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Syncup with the latest DT from the Linux kernel.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

For adding OCM memory in platform DTS is necessary to have reference to
amba bus.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add pinctrl node to DTSI.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Separate IRQ cells from each other for easier reading.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.
Signed-off-by: NNathan Sullivan <nathan.sullivan@ni.com>
Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The size of the GEM's register area is only 0x1000 bytes.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

To silence the warning
   cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Based on SPEC you right names with addresses.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

SLCR can be used for IP configuration setting.
Add SLCR skeleton to enable run time checking.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000).
No reason to use magic values 0 and 1.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Define a new config "zynqmp_ep" for ZynqMP instead
of xilinx_zynqmp. This defconfig supports all emulation
platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP
to ARCH_ZYNQMP.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Move the zynqmp Kconfig from board to arch
as there may be different boards under same
architecture.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This allows using devices plugged into both ports of the tablet.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

On some boards the otg is wired up in host-only mode in this case we
have no vbus-det gpio.

Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and
stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as
if a charger is plugged into the otg port.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Modify the sunxi musb glue to use the device-model for musb host mode.

This allows using musb in host mode together with other host drivers
such as ehci / ohci, which is esp. useful on boards which use the
musb controller in host-only mode, these boards have e.g. an usb-a
receptacle or an usb to sata converter attached to the musb controller.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Move the musb config and platdata to the sunxi-musb glue, which is where
it really belongs. This is preparation patch for adding device-model
support for the sunxi-musb-host code.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Add support for reading the id pin value of the otg connector to the usb
phy code.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Start using the new Kconfig options which are available for these now,
and simply always enable them by selecting them as sunxi builds always
include USB support.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NSimon Glass <sjg@chromium.org>

With certain features being convert to DM now we want sunxi to default
to having DM enabled for ETH/SERIAL and USB in some cases.

Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: NTom Rini <trini@konsulko.com>
[hdegoede@redhat.com: Also select CONFIG_USB for all sunxi builds]
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NSimon Glass <sjg@chromium.org>

At one point in time the utoo-p66 dts file in the kernel had a bogus
uart entry, and it seems like we synced with the kernel at just the wrong
moment.

This commit removes the bogus uart entry, which breaks booting the utoo-p66
when DM_SERIAL=y.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND
memory and SD card. Detection where SPL was read from is implemented in
`spl_boot_device`.
Signed-off-by: NDaniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Some small coding style fixes]
Acked-by: NHans De Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This patch extracts checking for valid SD card "eGON.BT0" signature from
`board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`.

Buffer for mmc sector is allocated and freed at runtime. `panic` is
triggered on malloc failure.
Signed-off-by: NDaniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0]
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since
I don't know of a way to test the boot-device upon runtime, this patch
hardcodes the spl_boot_device instead.

Tested on Marvell DB-88F6820-GP board.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>

This I2C device is used SoC-internally for controlling the DMD core.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

For the record, describe exactly which device of which vendor
is used on this board.

I2C EEPROM is bound by the generic compatible string, "i2c-eeprom",
so this commit has no impact on the functionality.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Remove the incorrect PEX macros from the DDR header. And insert the
correct ones in ctrl_pex.h instead.
Signed-off-by: NStefan Roese <sr@denx.de>

With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

     drivers/ddr/marvell/axp
     Supporting Armada XP (AXP) devices (and perhaps Armada 370)

     drivers/ddr/marvell/a38x
     Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: NStefan Roese <sr@denx.de>

This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: NStefan Roese <sr@denx.de>