- 10 8月, 2017 1 次提交
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由 Santan Kumar 提交于
Smart voltage translator is removed from LS2080ARDB/LS2088ARDB RevF boards. It is only used on LS2081ARDB. Programming GPIO is only required for LS2081ARDB. Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> [YS: Revise commit message] Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 06 6月, 2017 1 次提交
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由 Simon Glass 提交于
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: NSimon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 02 6月, 2017 1 次提交
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由 Bogdan Purcareata 提交于
DPAA2 platforms boot the Management Complex based on the u-boot env variable "mcinitcmd". Instead of doing this step on each platform individually, define a single mc_env_boot function in the MC driver, since it's semantically tied to it. Call the function in a per-board reset_phy hook, as it gets called at a later moment, when all board PHY devices have been initialized. Signed-off-by: NBogdan Purcareata <bogdan.purcareata@nxp.com> Signed-off-by: NHeinz Wrobel <heinz.wrobel@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 24 5月, 2017 6 次提交
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由 Udit Agarwal 提交于
This patch adjusts memory map for secure boot headers on LS2080AQDS and LS2080ARDB platforms. Secure boot headers are placed on NOR flash at offset 0x00600000. Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Santan Kumar 提交于
This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
LS2081ARDB board is similar to LS2080ARDB board with few differences It hosts LS2081A SoC Default boot source is QSPI-boot It does not have IFC interface RTC and QSPI flash device are different It provides QIXIS access via I2C Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled. In case QIXIS code is not enabled, use default sysclk value as 100MHz per board documentation. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 25 4月, 2017 1 次提交
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由 Santan Kumar 提交于
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 13 4月, 2017 1 次提交
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由 Simon Glass 提交于
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 06 4月, 2017 2 次提交
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由 Simon Glass 提交于
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Glass 提交于
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NStefan Roese <sr@denx.de>
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- 29 3月, 2017 1 次提交
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由 Santan Kumar 提交于
Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 28 3月, 2017 1 次提交
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由 Udit Agarwal 提交于
Moves sec_init to board_init rather than in misc_init function beacuse PPA will be initialised in board_init function and for PPA validation sec_init has to be done prior to PPA init. Signed-off-by: NSumit Garg <sumit.garg@nxp.com> Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 14 3月, 2017 2 次提交
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由 York Sun 提交于
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: NYork Sun <york.sun@nxp.com>
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- 24 1月, 2017 1 次提交
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由 Tom Rini 提交于
Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 16 12月, 2016 1 次提交
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由 Shengzhou Liu 提交于
Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 23 11月, 2016 1 次提交
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由 Priyanka Jain 提交于
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 17 11月, 2016 2 次提交
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由 Alexander Graf 提交于
The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's rather claim it's a reserved region in the EFI memory map Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Alexander Graf 提交于
On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com> [agraf: Fix x86 build]
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- 28 9月, 2016 1 次提交
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由 Sriram Dash 提交于
The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
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- 15 9月, 2016 1 次提交
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由 York Sun 提交于
Debug server feature has been dropped from roadmap. Signed-off-by: NYork Sun <york.sun@nxp.com>
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- 16 7月, 2016 1 次提交
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由 York Sun 提交于
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: NYork Sun <york.sun@nxp.com>
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- 13 6月, 2016 1 次提交
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由 Sriram Dash 提交于
This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: NSriram Dash <sriram.dash@nxp.com> Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
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- 11 6月, 2016 1 次提交
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Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 04 6月, 2016 3 次提交
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由 Prabhakar Kushwaha 提交于
SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
U-Boot should continue to work without management complex (MC). Fix compiling errors and warnings. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 Shengzhou Liu 提交于
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 18 5月, 2016 2 次提交
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由 Prabhakar Kushwaha 提交于
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shengzhou Liu 提交于
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 07 4月, 2016 1 次提交
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由 York Sun 提交于
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: NYork Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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- 29 3月, 2016 2 次提交
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由 Rai Harninder 提交于
This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: NRai Harninder <harninder.rai@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Saksham Jain 提交于
Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: NSaksham Jain <saksham.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 25 3月, 2016 1 次提交
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由 Stuart Yoder 提交于
The fsl-mc node has been moved under /soc, so update the path references accordingly. Backwards compatibility is retained for /fsl-mc. Delete backwards compatibility for the completely obsolete /fsl,dprc@0. Signed-off-by: NStuart Yoder <stuart.yoder@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 22 3月, 2016 2 次提交
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由 Prabhakar Kushwaha 提交于
As phy_connect and phy_config are being called from DPAA2 driver. Remove calling of mentioned function from board file. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 06 2月, 2016 1 次提交
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由 Bin Meng 提交于
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 15 12月, 2015 1 次提交
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由 York Sun 提交于
MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: NYork Sun <yorksun@freescale.com>
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