Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
Reviewed-by: NDinh Nguyen <dinguyen@kernel.org>

The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.
Signed-off-by: NMarek Vasut <marex@denx.de>

Signed-off-by: NMarek Vasut <marex@denx.de>

The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: NMarek Vasut <marex@denx.de>

Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
      which point this will likely need further rework.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>

Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NPavel Machek <pavel@denx.de>

Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: NPavel Machek <pavel@denx.de>