- 28 1月, 2017 3 次提交
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由 Tang Yuantian 提交于
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tang Yuantian 提交于
The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tang Yuantian 提交于
The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 27 1月, 2017 1 次提交
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- 26 1月, 2017 12 次提交
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由 Ladislav Michl 提交于
Currently maximum volume size can be specified only if no other arguments are used. Use '-' placeholder as volume size to allow maximum volume size to be specified together with volume id and type. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
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由 Simon Glass 提交于
This is not used in U-Boot, and the only usage calls a non-existent function. Drop it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Rather than having an arch-specific function, use the existing generic one. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is only called from one place and the function cannot be inlined. Convert it to a normal function. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is not defined anywhere in U-Boot. Drop this dead code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
To avoid an unnecessary arch-specific call in board_init_f(), rename this function. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This converts the following to Kconfig: CONFIG_ARCH_MISC_INIT Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This converts the following to Kconfig: CONFIG_ARCH_EARLY_INIT_R Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is not defined by any board in U-Boot. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 25 1月, 2017 13 次提交
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由 Konstantin Porotchkin 提交于
Update the MMC block device access code in bubt command implementation according to the latest MMC driver changes. Change-Id: Ie852ceefa0b040ffe1362bdb7815fcea9b2d923b Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
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由 Stefan Roese 提交于
This patch enables the MMC support for the SDHCI controller on the Armada 7k db-88f7040 and the Armada 8k db-88f8040 board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This patch adds the SDHCI device tree nodes to the Armada 7040-db dts file. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This patch adds the SDHCI device tree nodes to the Armada AP806 dtsi file which is used by the Armada 7k/8K SoCs. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This patch enables the MMC support for the SDHCI controller on the Armada 3700 db-88f3720 board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This patch adds the SDHCI device tree nodes to the Armada 3700-db dts file. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This patch adds the SDHCI device tree nodes to the Armada 3700 dtsi file. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
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由 Stefan Roese 提交于
This driver implementes platform specific code for the Xenon SDHCI controller which is integrated in the Marvell MVEBU Armada 37xx and Armada 7k / 8K SoCs. History: This driver is ported from the Marvell U-Boot version 2015.01 which is written by Victor Gu <xigu@marvell.com> with minor changes ported from the Linux driver which is written by Ziji Hu <huziji@marvell.com>. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Stefan Roese 提交于
Some SDHCI drivers might need to do some special controller configuration after the common clock set_ios() function has been called (speed / width configuration). This patch adds a call to the newly created function set_ios_port() when its configured in the host driver. This will be used by the Xenon SDHCI controller driver used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Stefan Roese 提交于
This patch completely clears the SDHCI_CLOCK_CONTROL register before the new value is configured instead of just clearing the 2 bits SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some clock configurations will lead to the "Internal clock never stabilised." error message on the Xenon SDHCI controller used on the Marvell Armada 3700 and 7k/8k ARM64 SoCs. The Linux SDHCI core driver also writes 0 to this register before the new value is configured. So this patch simplifies the driver a bit and brings the U-Boot driver more in-line with the Linux one. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Tony O'Brien 提交于
Commit ac337168 unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f9 for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: NChris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: NTony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
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由 Tony O'Brien 提交于
The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: NHamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: NTony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Darwin Dingel 提交于
Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: NChris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: NDarwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: York Sun <york.sun@nxp.com> [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 24 1月, 2017 9 次提交
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由 Tom Rini 提交于
As part of 1905c8fc we introduced failures depending on if swig and libpython-dev are installed or not. To provide coverage for this are of code in the future ensure we have these packages installed. Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Andrew F. Davis 提交于
Currently all secure media types of SPL are generated for all platforms, all platforms do not need all types, only generate the media types valid for each platform. Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Tested-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Tom Rini 提交于
When we have python building tools for the host it will not check HOSTXX variables but only XX variables, for example LDFLAGS and not HOSTLDFLAGS. Cc: Simon Glass <sjg@chromium.org> Reported-by: NHeiko Schocher <hs@denx.de> Fixes: 1905c8fc ("build: Always build the libfdt python module") Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Tested-by: NHeiko Schocher <hs@denx.de>
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由 Cédric Schieli 提交于
In commit c2e7e72b, the ramdisk relocation code was moved from image_setup_linux to do_bootm, leaving the bootz and booti cases broken. This patch fixes both by adding the BOOTM_STATE_RAMDISK state in their call to do_bootm_states if CONFIG_SYS_BOOT_RAMDISK_HIGH is set. Signed-off-by: NCédric Schieli <cschieli@gmail.com> Reviewed-by: NRick Altherr <raltherr@google.com> Tested-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Uri Mashiach 提交于
The module is continuously rebooting with the following message: Net: data abort pc : [<fff77f42>] lr : [<fff6e32b>] reloc pc : [<80816f42>] lr : [<8080d32b>] sp : fdf5ce48 ip : fdf5d79c fp : 00000017 r10: 8083cd58 r9 : fdf5cef0 r8 : fdf5d5d0 r7 : 48485000 r6 : 400000ff r5 : fdf5d6e0 r4 : fdf5d618 r3 : fdf5d5b4 r2 : fdf5d5d0 r1 : 643a3631 r0 : fdf5d6e0 Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Modifications: * Enable Ethernet configuration in the SPL. * Update PINMUX of PHY enable GPIO. Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: NTom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
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由 Tom Rini 提交于
Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tom Rini 提交于
Rename CONFIG_IMX31_PHYCORE_EET to CONFIG_TARGET_IMX31_PHYCORE_EET and make this a distinct config target. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tuomas Tynkkynen 提交于
The directory structure of device tree files produced by the kernel's 'make dtbs_install' is different on ARM64, the RPi3 device tree file is in a 'broadcom' subdirectory there. Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org>
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- 23 1月, 2017 2 次提交
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由 Jagan Teki 提交于
Print the error code for non-zero (failure case) instead of making debug statement without any condition, this usually gives proper clue in failure condition. Log:
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由 Stefan Herbrechtsmeier 提交于
The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. The Linux kernel distinguishes between base clock (max_clk) of the host controller and maximum frequency (f_max) of the card interface. Use the same differentiation and allow the platform to constrain the peripheral interface. Signed-off-by: NStefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
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