- 08 10月, 2019 40 次提交
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由 Jacky Bai 提交于
On, i.MX8MQ, the PLL config must be done when ddrmix isolation is released. So move the dram pll init after iso config done. For other i.MX8M SOC, either init pll before or after isolation is ok. Signed-off-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Jacky Bai 提交于
Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: NJacky Bai <ping.bai@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Bai Ping 提交于
Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: NBai Ping <ping.bai@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Tested-by: NRobby Cai <robby.cai@nxp.com>
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由 Ye Li 提交于
Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Add the compatible string and driver data for iMX7ULP platform Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Ye Li 提交于
Add the driver data for each compatible string. So we can remove the SOC config and use driver data instead. Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Ye Li 提交于
The write data size can be overwritten by writing to the IDATSZ field of IPCR register. Since the driver always updates the IDATSZ in page program operation. Set the LUT data size to 0 to align the codes with iMX. Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Ye Li 提交于
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Parthiban Nallathambi 提交于
conditionally include long help text when enabled Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Parthiban Nallathambi 提交于
board early initialize fec ethernet controller pinmux only when FEC is enabled Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Parthiban Nallathambi 提交于
boot order was added to handle both SD and eMMC. But commit 14d319b1 introduced to handle both eMMC and SD globally. Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Parthiban Nallathambi 提交于
Booting from NAND needs nandbcb and nand boot device selection Signed-off-by: NParthiban Nallathambi <pn@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Igor Opaniuk 提交于
Use distro_bootcmd as default bootcmd instead of legacy wrappers. Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Igor Opaniuk 提交于
Use distro_bootcmd as defauult bootcmd instead of legacy wrappers. Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
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由 Peng Fan 提交于
Add more scfw api for clk/partition/seco usage The api will be used by ccf/partition/secure boot. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8 only support AHAB secure boot with Container format image, we could not use FIT to support secure boot, so introduce container support to let SPL could load container images. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
After u-boot.cnt is padded to flash.bin automatically by script, no need to burn the image mannually, so drop the step. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use flexible offset which is calculated based on the size of the container image generated int the first stage. And pad u-boot.cnt at 1KB alignment. So add code to get the offset when SPL loading u-boot.cnt. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Introduce weak spl_nand_get_uboot_raw_page, then platform could have their own implementation. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Andreas Dannenberg <dannenberg@ti.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Michal Simek <michal.simek@xilinx.com>
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由 Peng Fan 提交于
Introduce weak spl_nor_get_uboot_base, then platform have their own implementation. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Andreas Dannenberg <dannenberg@ti.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Michal Simek <michal.simek@xilinx.com>
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由 Peng Fan 提交于
Introduce a weak function spl_spi_get_uboot_offs, then platform could have their own implementation. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Andreas Dannenberg <dannenberg@ti.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Michal Simek <michal.simek@xilinx.com>
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由 Peng Fan 提交于
Introduce a weak function spl_mmc_get_uboot_raw_sector, then platform could have their own implementation. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Andreas Dannenberg <dannenberg@ti.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Michal Simek <michal.simek@xilinx.com>
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由 Peng Fan 提交于
Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Import i.MX8MM pin func from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Import i.MX8MM dtsi from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Because we need to get cpu freq in print_cpuinfo at very early stage, so we need to make sure the ccm be probed. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port. To directly return devno, we could avoid add board specific code. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MQ and i.MX8MM has totally different pll design, so rename clock to clock_imx8mq. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Make reset_cpu only visible when CONFIG_SYSRESET not defined or CONFIG_SPL_BUILD. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
To i.MX8MM SCTR clock is disabled by ROM, so before timer init need to enable it. To i.MX8MQ, it does not hurt the clock is enabled again. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Set trustzone region 0 to allow both non-secure and secure access when trust zone is enabled. We found USB controller fails to access DDR if the default region 0 is secure access only. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE memory from its settings. So ARM speculative prefetch in u-boot may access that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory is set to secure access, then the speculative prefetch will fail and cause various memory issue in u-boot. The fail address register and int_status register in trustzone has logged that speculative access from u-boot. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
There are several variants based on i.MX8MM, add the support in get_cpu_rev Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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