imx8mq: Update the ddrc QoS setting for B1 chip

Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.
Signed-off-by: NBai Ping <ping.bai@nxp.com>
Reviewed-by: NYe Li <ye.li@nxp.com>
Tested-by: NRobby Cai <robby.cai@nxp.com>

board/freescale/imx8mq_evk/lpddr4_timing.c

@@ -72,8 +72,10 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
 	{ DDRC_SCHED(0), 0x29511505 },
 	{ DDRC_SCHED1(0), 0x0000002c },
 	{ DDRC_PERFHPR1(0), 0x5900575b },
-	{ DDRC_PERFLPR1(0), 0x00000009 },
-	{ DDRC_PERFWR1(0), 0x02005574 },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
 	{ DDRC_DBG0(0), 0x00000016 },
 	{ DDRC_DBG1(0), 0x00000000 },
 	{ DDRC_DBGCMD(0), 0x00000000 },
@@ -83,10 +85,12 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
 	{ DDRC_PCFGR_0(0), 0x000010f3 },
 	{ DDRC_PCFGW_0(0), 0x000072ff },
 	{ DDRC_PCTRL_0(0), 0x00000001 },
-	{ DDRC_PCFGQOS0_0(0), 0x01110d00 },
-	{ DDRC_PCFGQOS1_0(0), 0x00620790 },
-	{ DDRC_PCFGWQOS0_0(0), 0x00100001 },
-	{ DDRC_PCFGWQOS1_0(0), 0x0000041f },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
 
 	/* Frequency 1: 400mbps */
 	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },

drivers/ddr/imx/imx8m/lpddr4_init.c

@@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing)
 	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
 
 	debug("DDRINFO: cfg clk\n");
-	dram_pll_init(MHZ(750));
+	if (is_imx8mq())
+		dram_pll_init(MHZ(800));
+	else
+		dram_pll_init(MHZ(750));
 
 	/*
 	 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,