imx8mq: Update the ddrc QoS setting for B1 chip
Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: NBai Ping <ping.bai@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Tested-by: NRobby Cai <robby.cai@nxp.com>
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