- 20 7月, 2019 26 次提交
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由 Marek Vasut 提交于
Use CONFIG_IS_ENABLED(WDT) to permit use of WDT in SPL without DM, while the full U-Boot can use rich DM/DT WDT driver. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: NHeiko Schocher <hs@denx.de> Tested-by: NSuniel Mahesh <sunil.m@techveda.org>
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由 Lukasz Majewski 提交于
Before the wide DM/DTS adoption in the U-Boot proper, the display5 has been using only DM_SERIAL to provide serial console in pre-relocation. After moving to full DM/DTS adoption in the U-Boot proper the U_BOOT_DEVICE definition is not needed anymore, as it has been replaced with udevice creation from provided DTS description. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
This file setups UART5 based serial to be used as pre-relocation console in the U-Boot proper. On purpose pinux configuration is omitted here as it has been already done in SPL. For early pre-relocation code we only need the serial device from DTS. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
This commit ports from Linux kernel - tag: v5.1 - the device tree description for display5 board. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
Porting more DTS code from Linux kernel for display5 board required increase of pre-relocation malloc pool size in U-Boot proper. The early malloc memory is necessary for handling parsing and setup of e.g. serial port device (and all its ancestors in DT tree). Signed-off-by: NLukasz Majewski <lukma@denx.de> Acked-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
Add missing parenthesis to the GPIO_TO_PORT macro. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
After commit 14453fbf ("Convert CONFIG_SF_DEFAULT_* to Kconfig") and commit abe66b1b ("Convert CONFIG_ENV_SPI_* to Kconfig") ,which moved some SPI related CONFIG_* defines to Kconfig the display5 board has become unbootable as the SPI CS check condition had wrong value. This commit fixes this check and allows proper SPI NOR flash operation in SPL. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
This commit just corrects spelling of 'accessed' word in the EEPROM comment. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Lukasz Majewski 提交于
Some comments are not needed anymore after Kconfig automated conversion. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Shyam Saini 提交于
This would be used for writing spl images along nand BCB Signed-off-by: NShyam Saini <shyam.saini@amarulasolutions.com>
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由 Shyam Saini 提交于
SPL on Engicam i.Core M6 boards enabled DM, so it would require some malloc() pool before relocation in order to load U-Boot proper properly. So, enable SPL malloc() pool of 0x2000 size similarly like what we have used for icore mmc defconfigs. Signed-off-by: NShyam Saini <shyam.saini@amarulasolutions.com>
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由 Heiko Schocher 提交于
add DM support for pwm-imx driver. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Heiko Schocher 提交于
add Kconfig support for this driver. Signed-off-by: NHeiko Schocher <hs@denx.de> Acked-by: NMartyn Welch <martyn.welch@collabora.co.uk>
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由 Sébastien Szymanski 提交于
This function sets the polarity of the PWR signal which is not used on the opos6uldev board. Remove it. Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NSébastien Szymanski <sebastien.szymanski@armadeus.com>
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由 Lukasz Majewski 提交于
This commit updates the doc/README.falcon regarding Falcon boot on NOR flash memories. This code is used by MCCMON6 board - so for more details please refer to configs/mccmon6_nor_defconfig. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
This option will provide the offset in the parallel NOR flash memory to, which the falcon boot data is stored. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
The CMD_SPL_NAND_OFS description was a bit misleading, has been updated. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
This commit makes the CMD_SPL_NAND_OFS only visible when we use NAND memory. Before this change it was present when only CMD_SPL was enabled (and would stay when board with other falcon boot medium is used). Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
mccmon6 works in 10/100 MiB Ethernet environment, so disabling 1GiB support improves robustness of the network after power up (as one don't need to wait for autoneg). Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
The IMX6Q based MCCMON6 is not using USB for any purpose. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
This comment is a leftover from the Kconfig CONFIG_*MTD* move. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Ye Li 提交于
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz. We update DDR clock relevant settings to approach the target. But since the limitation on LCDIF pix clock for HDMI output (refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR clock to 352.8Mhz (25.2Mhz * 14) by using the clock path: APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept, so the divider 14 is calculated as: 14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1) NIC0_DIV: 1 NIC1_DIV: 0 LCDIF_PCC_DIV: 6 APLL and APLL PFD0 settings: PFD0 FRAC: 27 APLL MULT: 22 APLL NUM: 1 APLL DENOM: 20 This patch applies the new settings for both DCD and plugin. There is no DDR script change on this new frequency. Overnight memtester is passed. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Due to the APLL out glitch issue, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design. Signed-off-by: NYe Li <ye.li@nxp.com> Acked-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate. The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus. Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings: PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5 Signed-off-by: NYe Li <ye.li@nxp.com> Tested-by: NFancy Fang <chen.fang@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Update LPDDR3 script with the changes below: -Update the precharge command to CMD=01 at the DDR initialization phase -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn Test: One EVK board passes overnight stress test. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule. Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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- 19 7月, 2019 14 次提交
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由 Bryan O'Donoghue 提交于
If no CONFIG_OPTEE_LOAD_ADDR is provided i.e. you are not loading OPTEE into memory in u-boot, then just set the non-existent CONFIG option to zero, elsewise stringify(CONFIG_OPTEE_LOAD_ADDR) will return "CONFIG_OPTEE_LOAD_ADDR" - which looks weird in the u-boot environment. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
In the Mbed Linux OS bootflow OP-TEE runs before u-boot and provides a DTB overlay at 0x83100000. This overlay should subsequently be merged into the main DTB before handing over to the kernel. This patch defines fdtovaddr at 0x83100000. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
This commit enables CONFIG_OF_LIBFDT_OVERLAY a requirement to perform a merge of an OPTEE provided DTB overlay into our main kernel DTB image. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
In order to switch on DTB overlay support in WaRP7 BL33 we first need to switch on LIBFDT support. Do that now. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
Reusing the loadaddr to load the boot script breaks some of the logic we want to have around the bootscript/FIT load addresses. Making a dedicated bootscript address allows us to differentiate the bootscript load address from the Linux Kernel or OPTEE load address, thus ensuring that no matter what the load sequence the bootscript and Kernel/OPTEE binary load addresses do not conflict. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
When obtaining the bootscript from a FIT image we need to specify the name of the bootscript as defined inside of the FIT. This patch makes a define that appends a "bootscr" parameter to the source command when compiling up in FIT mode on warp7. An environment variable is supplied to enable others to use a different name than "bootscr" as the image name of the boot script in their FIT. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Bryan O'Donoghue 提交于
This patch switches on FIT verification of boot.scr. After this commit your boot.scr must be in the FIT format. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org>
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由 Matti Vaittinen 提交于
BD71837 and BD71847 is PMIC intended for powering single-core, dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847 is used for example on NXP imx8mm EVK. Add regulator driver for ROHM BD71837 and BD71847 PMICs. BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version containing 6 bucks and 6 LDOs. Voltages for DVS bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted when regulators are enabled. For other bucks and LDOs we may have over- or undershooting if voltage is adjusted when regulator is enabled. Thus this is prevented by default. BD718x7 has a quirk which may leave power output disabled after reset if enable/disable state was controlled by SW. Thus the SW control is only allowed for BD71837 bucks 3 and 4 by default. The impact of this limitation must be evaluated board-by board and restrictions may need to be modified. (Linux driver get's these limitations from DT and we may want to implement same on u-Boot driver). Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Peng Fan 提交于
Add thermal dts node Enable thermal in defconfig Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8 thermal driver to support get temperature from SCU. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add sc_misc_get_temp to support get temperature Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Bryan O'Donoghue 提交于
Commit 32ce6179 ("optee: Add lib entries for sharing OPTEE code across ports") adds code into lib/optee but neglects to update MAINTAINERS to make me buggable for questions and maintenance. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org> Suggested-by: NJens Wiklander <jens.wiklander@linaro.org>
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由 Bryan O'Donoghue 提交于
When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the following print-out. Board: WARP7 in secure mode OPTEE DRAM 0xa0000000-0xa0000000 This is incorrect the right range is 0x9e000000-0xa0000000. This patch fixes the defines on the warp7_bl33_defconfig file to tidy up the output. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com>
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由 Bryan O'Donoghue 提交于
Commit c7b3a7ee ("optee: adjust dependencies and default values for dram") makes the TZDRAM defines for OPTEE show up for all configs as a side-effect. While not harmful its not what we really want. This patch makes the following defines contingent on CONFIG_OPTEE=y CONFIG_OPTEE_TZDRAM_BASE CONFIG_OPTEE_TZDRAM_SIZE Rightly, if you don't have CONFIG_OPTEE=y you don't care about the above two defines. Signed-off-by: NBryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Rui Miguel Silva <rui.silva@linaro.org> Acked-by: NRui Miguel Silva <rui.silva@linaro.org>
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