- 09 11月, 2018 1 次提交
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由 Stefan Roese 提交于
Testing has shown that a line-break is missing in one debug line in fit_find_config_node(). Signed-off-by: NStefan Roese <sr@denx.de>
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- 08 11月, 2018 3 次提交
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由 Bin Meng 提交于
Due to revert of commit c0434407, this board does not build any more. Disable CONFIG_DISPLAY_CPUINFO for v2018.11 release. This commit should be reverted after v2018.11 release. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This reverts commit c0434407. It turns out commit c0434407 broke some boards which have DM CPU driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail to boot when print_cpuinfo() is called during boot. Fixes are already sent to ML and in u-boot-dm/next, however since we are getting close to the v2018.11 release, it's safer we revert the original commit. This commit should be reverted after v2018.11 release. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 07 11月, 2018 4 次提交
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git://git.denx.de/u-boot-microblaze由 Tom Rini 提交于
Xilinx fixes for v2018.11-rc3 - Fix fit loading address for Zynq
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由 Michal Simek 提交于
Default setup is 0 which is incorrect place because it points to OCM which is allocated for SPL only in our case. Use address in DDR. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Paul Davey 提交于
Add local size_t variable to crypto_comp_decompress as intermediate storage for destination length to avoid memory corruption and incorrect results on 64 bit targets. This is what linux does for the various lz compression implementations. Signed-off-by: NPaul Davey <paul.davey@alliedtelesis.co.nz> Cc: Heiko Schocher <hs@denx.de> Tested-by: NHeiko Schocher <hs@denx.de>
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- 06 11月, 2018 13 次提交
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由 Stefan Roese 提交于
The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the theadorable Armada-XP board. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With patch 49b23e03 (pci: mvebu: Increase size of PCIe default mapping) the mapping size for each PCI(e) controller was increased from 32MiB to 128MiB. This leads to problems on boards with multiple PCIe slots / ports which are unable to map all PCIe ports, e.g. the Armada-XP theadorable: DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled) SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Cannot add window '4:f8', conflicts with another window PCIe unable to add mbus window for mem at f0000000+08000000 Model: Marvell Armada XP theadorable This patch moves the base address for the PCI(e) memory spaces from 0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now). This gives move room and flexibility for PCI(e) mappings. Signed-off-by: NStefan Roese <sr@denx.de> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: VlaoMao <vlaomao at gmail.com>
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由 Peng Fan 提交于
Add NXP linux team upstream maillist as reviewer Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Fabio Estevam 提交于
Commit 3c28576b ("arm: dts: imx8qxp: fix build warining") fixed the dts warning by removing the unnecessary #address-cells/#size-cells, but the recommendation for regulators is not to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator accordingly. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Fabio Estevam 提交于
board/freescale/mx8mq_evk/README has been introduced by mistake in commit d0dd7397 ("imx: add i.MX8QXP MEK board support") Remove it for now as this should be introduced when mx8mq_evk support is in place. Reported-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
If there is no CONTAINER entry, there is no need to flatten container header. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Fix: CID 184233: (NEGATIVE_RETURNS) Using variable "container" as an index to array "imx_header.fhdr". Reported-by: Coverity Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Fix: CID 184234: (TAINTED_SCALAR) Using tainted variable "header.num_images - 1" as an index into an array "header.img". Reported-by: Coverity Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Check lseek return value. Fix Coverity CID: 184236 184235 184232 Reported-by: Coverity Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com>
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由 Andy Shevchenko 提交于
New ACPI assembler issues a warning: board/intel/edison/dsdt.asl.tmp 13: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Indeed, in the OperationRegion the offset is 0x00 by default. Thus, drop unneeded Offset() use as suggested by ACPI assembler. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 04 11月, 2018 1 次提交
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- 03 11月, 2018 2 次提交
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git://git.denx.de/u-boot-mips由 Tom Rini 提交于
- replace the dynamic size of the relocation table with a fixed but configurable size - fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol
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由 Daniel Schwierzeck 提交于
Currently the size of the relocation table will be shrunk to the actual size needed. Although this gives a maximal space saving, it messes up the _end symbol. This breaks features like appended DTBs because the _end symbol doesn't point to the real end of the U-Boot binary. Remove the size shrinking and make the size of the relocation table fixed but configurable. This follows the Linux approach and the user can adjust the size to his needs. Also rename the relocation table section from .rel to .data.reloc to follow the Linux approach and to avoid ambiguities with the .rel.* sections added by the linker. Reported-by: NLars Povlsen <lars.povlsen@microsemi.com> Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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- 02 11月, 2018 15 次提交
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由 Marek Vasut 提交于
It is perfectly fine to write th DTCNTL TAP count and enable the SCC sampling clock operation in the same write. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
When the bus switches to 1.8V mode of operation, it is necessary to verify that the card correctly initiated and completed the voltage switch. This is done by reading out the state of DATA0 line. This patch implement support for reading out the state of the DATA0 line, so the MMC core code can correctly switch to 1.8V mode. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Make sure to clear HS400 configuration when resetting the SCC block. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add check to avoid touching the SCC tuning registers in case the IP doesn't support them or if the support isn't in place yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Preinitialize the SD card signals regulator to 3.3V, which is the default post-reset setting, to be sure the regulator is set to a valid value. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Configure the clock settings before reconfiguring any other IO settings. This is required when the clock must be stopped before changing eg. the pin configuration or any of the other properties of the bus. Running the clock configuration first allows the MMC core to do just that. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
In case the controller performs card tuning, that is, sends MMC command 19 or 21, silence possible CRC error warning prints. The warnings are bound to happen, since the tuning will fail for some settings while searching for the optimal configuration of the bus and that is perfectly OK. This patch passes around the MMC command structure and adds check into tmio_sd_check_error() to avoid printing CRC error warning when the tuning happens. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Properly handle return values and abort operations when they are non-zero. This is a minor improvement, which fixes two remaining unchecked return values. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400 modes all use 1.8V signaling, while all the legacy modes use 3.3V signaling. While there are extra modes which use 1.2V signaling, the existing hardware does not support those. Simplify the pinmux such that 3.3V signaling implies legacy mode pinmux and the rest implies UHS mode pinmux. This prevents the massive case statement from growing further. Moreover, it fixes an edge case where during SD 1.8V switch, the bus mode is still set to default while the signaling is already set to 1.8V, which results in an attempt to communicate with a 1.8V card using pins in 3.3V mode and thus communication failure. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec3476 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add definition of the POCCTRL register and bits therein to R8A77990 E3 pincontrol driver. This allows the pincontrol driver to configure SDHI pin voltage according to power-source DT property. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Use fixed 4bit size for generating the DRV register element mask, not the size of the value, which can be smaller. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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git://git.denx.de/u-boot-arc由 Tom Rini 提交于
Just 2 non-functinal changes: 1. Rename of EMDK to EMSDP so it matches real marketing name 2. Add essential README for IoTDK
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由 Alexey Brodkin 提交于
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Alexey Brodkin 提交于
Real marketing name of the board was recently updated so to accommodate that change renaming the board and all related to it. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 01 11月, 2018 1 次提交
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由 Sam Protsenko 提交于
This part should've been remove in commit 88d60db0 ("arm: ti: boot: Remove environment partition"), but I missed it somehow. Remove reading dtb file from environment partition on eMMC, as we don't have it anymore. Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>
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