Merge git://git.denx.de/u-boot-marvell

arch/arm/dts/armada-xp-theadorable.dts

@@ -134,7 +134,7 @@
 					u-boot,dm-pre-reloc;
 					#address-cells = <1>;
 					#size-cells = <1>;
-					compatible = "n25q128a13", "jedec,spi-nor";
+					compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
 					reg = <0>; /* Chip select 0 */
 					spi-max-frequency = <27777777>;
 				};
@@ -151,11 +151,11 @@
 			spi1: spi@10680 {
 				status = "okay";
 
-				fpga@2 {
+				fpga@0 {
 					#address-cells = <1>;
 					#size-cells = <1>;
 					compatible = "spi-generic-device";
-					reg = <2>; /* Chip select 2 */
+					reg = <0>; /* Chip select 0 */
 					spi-max-frequency = <27777777>;
 				};
 			};

arch/arm/mach-mvebu/dram.c

@@ -33,7 +33,9 @@ struct sdram_addr_dec {
 #define REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
 #define REG_CPUCS_WIN_SIZE(x)		(((x) & 0xff) << 24)
 
-#define SDRAM_SIZE_MAX			0xc0000000
+#ifndef MVEBU_SDRAM_SIZE_MAX
+#define MVEBU_SDRAM_SIZE_MAX		0xc0000000
+#endif
 
 #define SCRUB_MAGIC		0xbeefdead
 
@@ -275,8 +277,8 @@ int dram_init(void)
 		 * address space left for the internal registers etc.
 		 */
 		size += mvebu_sdram_bs(i);
-		if (size > SDRAM_SIZE_MAX)
-			size = SDRAM_SIZE_MAX;
+		if (size > MVEBU_SDRAM_SIZE_MAX)
+			size = MVEBU_SDRAM_SIZE_MAX;
 	}
 
 	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
@@ -312,7 +314,7 @@ int dram_init_banksize(void)
 
 		/* Clip the banksize to 1GiB if it exceeds the max size */
 		size += gd->bd->bi_dram[i].size;
-		if (size > SDRAM_SIZE_MAX)
+		if (size > MVEBU_SDRAM_SIZE_MAX)
 			mvebu_sdram_bs_set(i, 0x40000000);
 	}
 

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -68,10 +68,12 @@ enum {
 	MVEBU_SOC_UNKNOWN,
 };
 
+#define MVEBU_SDRAM_SIZE_MAX	0xc0000000
+
 /*
  * Default Device Address MAP BAR values
  */
-#define MBUS_PCI_MEM_BASE	0xE8000000
+#define MBUS_PCI_MEM_BASE	MVEBU_SDRAM_SIZE_MAX
 #define MBUS_PCI_MEM_SIZE	(128 << 20)
 #define MBUS_PCI_IO_BASE	0xF1100000
 #define MBUS_PCI_IO_SIZE	(64 << 10)