- 09 10月, 2020 23 次提交
-
-
由 Chee Hong Ang 提交于
Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Ley Foon Tan 提交于
Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com> Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
由 Ley Foon Tan 提交于
Sync latest mailbox response codes from SDM firmware. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com> Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
由 Chee Hong Ang 提交于
Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chin Liang See 提交于
Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: NChin Liang See <chin.liang.see@intel.com> Signed-off-by: NSiew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
由 Chee Hong Ang 提交于
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Enable sysreset support for Agilex platform. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chin Liang See 提交于
In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: NChin Liang See <chin.liang.see@intel.com> Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>
-
由 Chee Hong Ang 提交于
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
由 Ley Foon Tan 提交于
Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com> Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
由 Ley Foon Tan 提交于
Add get nand_clk and nand_x clock support. Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com> Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
-
- 08 10月, 2020 17 次提交
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash由 Tom Rini 提交于
- Fix devicetree address determination seen on QEMU ARM64 - Use DMA for reads is available
-
由 Andre Przywara 提交于
The cfi-flash driver uses an open-coded version of the generic algorithm to decode and translate multiple frames of a "reg" property. This starts off the wrong foot by using the address-cells and size-cells properties of *this* very node, and not of the parent. This somewhat happened to work back when we were using a wrong default size of 2, but broke about a year ago with commit 0ba41ce1 ("libfdt: return correct value if #size-cells property is not present"). Instead of fixing the reinvented wheel, just use the generic function that does all of this properly. This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding a wrong flash base address: DRAM: 1 GiB Flash: "Synchronous Abort" handler, esr 0x96000044 elr: 00000000000211dc lr : 00000000000211b0 (reloc) elr: 000000007ff5e1dc lr : 000000007ff5e1b0 x0 : 00000000000000f0 x1 : 000000007ff5e1d8 x2 : 000000007edfbc48 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 00000000000000f0 x6 : 000000007edfbc2c x7 : 0000000000000000 x8 : 000000007ffd8d70 x9 : 000000000000000c x10: 0400000000000003 x11: 0000000000000055 ^^^^^^^^^^^^^^^^ Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NStefan Roese <sr@denx.de>
-
由 Vignesh Raghavendra 提交于
When possible use DMA for reading from CFI flash, this provides upto 5x improvement in read performance with high speed CFI compliant flashes like HyperFlash. Code will gracefully fallback to CPU copy when DMA is unavailable. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com> Reviewed-by: NStefan Roese <sr@denx.de>
-
由 Vignesh Raghavendra 提交于
Caller would need gracefully handle failures of dma_get_device(), therefore reduce pr_err() to pr_debug() when DMA device is not found. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com> Reviewed-by: NStefan Roese <sr@denx.de>
-
https://gitlab.denx.de/u-boot/custodians/u-boot-mips由 Tom Rini 提交于
- mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
-
由 Stefan Roese 提交于
Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting. Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: NStefan Roese <sr@denx.de> Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
由 Aaron Williams 提交于
This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
This patch adds the coremask handling functions. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
Add header to handle Octeon fuse access. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Aaron Williams 提交于
This header includes common register defines and accessor functions. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
This patch enables USB support with some helpful commands, like fs support. Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Stefan Roese 提交于
Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-