Convert versatile to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert tegra to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert socfpga to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert vexpress to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert mx25 to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Convert highbank to use the commmon timer code.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Remove platform CONFIG_SYS_HZ definition for configs a-z*.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Remove platform CONFIG_SYS_HZ definition for configs A-Z*.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

The definitions for CONFIG_SYS_PROMPT are varied with little reason other
than to display the board name. Over half the definitions are "==> ", so
make this the default. The rest of the boards remain unchanged to avoid
breaking any external scripts expecting a certain prompt.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>

T4240QDS eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missing
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.

The peripherals used by this design are:
- DDR3 RAM with SPD support
- SPI NOR Flash as boot medium
- NAND Flash
- 2 PCIe busses (hosts 1 and 3)
- 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
- 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
  FPGA
- 2 HW I2C busses
- last but not least, the mandatory serial port

The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
support and was changed according to our design (that means essentially
removing what is not present on the designs and a few adaptations).

There is currently only one prototype board that is based on this design
and this patch also introduces it. The board is called kmlion1.
Signed-off-by: NStefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

kmp204x: update the ENV #define

The comments had to be refined as well as the total size
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix ddr.c]
Acked-by: NYork Sun <yorksun@freescale.com>

This must be defined by a board support file that want to use the
keymile common.c board_eth_init function that requires ethernet_present
to be defined.

Currently all the km architectures use it but the kmp204x architecture
later supported in this series does use another board_eth_init function
and thus does not define it.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

This must be defined for all the keymile boards that use the common
i2c_abort function that is used to "reset" the I2C bus. These are
currently km82xx and km_arm boards.

The  km83xx boards use other functions and thus do not need this.

This patch removes the CONFIG_SYS_I2C_INIT_BOARD from keymile-common.h
and defines it for km_arm.h and km82xx.h.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

The ip kernel parameter had a typo in it (we've been lucky that it has
worked until now).
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

It must be set to a different value for the later add kmp204x
architecture, because we are restricted to 1MB SRAM.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

c29xpcie REV_A board DDR ECC chip has bad impedance in hardware,
force that kind of board to be DDR ECC off when booting.
Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on
in uboot enviroment.
Signed-off-by: NPo Liu <Po.Liu@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_TMU_CLK_FREQ,
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

arm: rmobile: kzm9g: Change clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

Previously, only host1 was supported using an index of 0.
Now, otg has index 0, host1 is 1, host2 is 2, host3 is 3.
Since OTG requires usbmode to be set after reset, I added
CONFIG_EHCI_HCD_INIT_AFTER_RESET to nitrogen6x.h and
mx6qsabreauto.h.

I also added a weak function board_ehci_power to handle
turning power on/off for otg.

Type is type of device connected (USB stick vs Host.)
Init is type of device desired.
Only power up port if type == init == USB_INIT_HOST.
Only return error if type != init.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>

Add the support for the am437x xhci usb host.

The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: NDan Murphy <dmurphy@ti.com>

Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: NDan Murphy <dmurphy@ti.com>

A set of environment variables needs to be updated to provide support for
TIZEN download command (tizendown).

Since DFU is used as a flashing backend, it is also necessary to extent
malloc pool size for DFU buffer allocation.
Moreover, for compatibility reasons (Win vs. Lin) new USB idProduct number
for download gadget had to be added.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Also, add other USB related config items.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>

This enables support for xHCI host controller on Exynos5
and further disables EHCI support, to make sure only one
host controller is enabled at a time, since right now
using two controllers at a time is not possible with
current usb core infrastructure.

Anyone who wants to enable EHCI support again needs to
enable CONFIG_USB_EHCI, CONFIG_USB_EHCI_EXYNOS once again
in exynos5-dt config.
Signed-off-by: NVikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>

XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>

Signed-off-by: NPhilippe Reynes <tremyfr@yahoo.fr>

This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to
CONFIG_SH_TMU_CLK_FREQ for boards.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

- Rename old P1010RDB board as P1010RDB-PA.
- Add support for new P1010RDB-PB board.
- Some optimization.

For more details, see board/freescale/p1010rdb/README.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix conflicts in boards.cfg]
Acked-by: NYork Sun <yorksun@freescale.com>

Since pins multiplexing, SDHC shares signals with IFC, with this patch:
To enable SDHC in case of NOR/NAND/SPI boot
   a) For temporary use case in runtime without reboot system
      run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
   b) For long-term use case
      set 'esdhc' in hwconfig and save it.
To enable IFC in case of SD boot
   a) For temporary use case in runtime without reboot system
      run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
   b) For long-term use case
      set 'ifc' in hwconfig and save it.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>

T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: NYork Sun <yorksun@freescale.com>

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

For USB device-tree fix-up to work properly, its necessary to
mention USB1 options before that of USB2 inside default hwconfig
string
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>

Current IFC timings for NAND flash are not able to support existing
K9F1G08U0B and new K9F1G08U0D flash.

so Update the timings to support both.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

Enable TPL for p1_p2_rdb_pc nand boot.
Signed-off-by: NYing Zhang <b40530@freescale.com>

Enable p1_p2_rdb_pc to start from eSPI with SPL.
Signed-off-by: NYing Zhang <b40530@freescale.com>

Enable p1_p2_rdb_pc to start from eSDHC with SPL.
Signed-off-by: NYing Zhang <b40530@freescale.com>

This patch re-config the NOR flash timing parameters which could make
the ifc timing more flexible for NOR flash.
The new parameters could fix the problem of hanging at "Flash:"
occasionally when booting the board.
Signed-off-by: NPo Liu <Po.Liu@freescale.com>

This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.
Signed-off-by: NPo Liu <Po.Liu@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: NTom Rini <trini@ti.com>