- 15 8月, 2017 2 次提交
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由 Jagan Teki 提交于
OLimex A64-OLinuXino is an open-source hardware board using the Allwinner A64 SOC. OLimex A64-OLinuXino has - A64 Quad-core Cortex-A53 64bit - 1GB or 2GB RAM DDR3L @ 672Mhz - microSD slot and 4/8/16GB eMMC - Debug TTL UART - HDMI - LCD - IR receiver - 5V DC power supply Tested-by: NJagan Teki <jagan@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
NanoPi A64 is a new board of high performance with low cost designed by FriendlyElec., using the Allwinner A64 SOC. Nanopi A64 features - Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS - 1GB DDR3 RAM - MicroSD - Gigabit Ethernet (RTL8211E) - Wi-Fi 802.11b/g/n - IR receiver - Audio In/Out - Video In/Out - Serial Debug Port - microUSB 5V 2A DC power-supply Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Tested-by: NJagan Teki <jagan@amarulasolutions.com>
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- 12 8月, 2017 1 次提交
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由 Jagan Teki 提交于
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi Here is the Linux last merge tag details: Merge: 0e91f43d e5770b7 Author: Stephen Rothwell <sfr@canb.auug.org.au> Date: Fri Jun 9 14:59:55 2017 +1000 Merge remote-tracking branch 'staging/staging-next' Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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- 11 8月, 2017 6 次提交
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由 Icenowy Zheng 提交于
The Ethernet function is enabled in the Orange Pi PC2 device tree and defconfig, however, CONFIG_MACPWR is not properly set, which left the PHY being disabled when booting, which makes the Ethernet function not usable. Add the proper value of this option in the PC2 defconfig. Fixes: e7bd15ea ("sunxi: Add OrangePi PC 2 initial support") Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Icenowy Zheng 提交于
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM. Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure. Add code to switch the PRCM to non-secure. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Icenowy Zheng 提交于
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in the PRCM header file. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Tested-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Clément Bœsch 提交于
Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi without heatsink results in the following error after a few minutes: WRITE FAILURE: 0x00200000 != 0xffdfffff at offset 0x0137f47c (bitflip). Also, the constructor repository (github/orangepi-xunlong) seems to contain that 624 Mhz clock speed in its u-boot fork. It may be that 672 Mhz is the advertized overclocked speed. According to http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit it may be worth decreasing that value with other Orange Pi boards. See also e7d6aa0b. Signed-off-by: NClément Bœsch <u@pkh.me> [Add s-o-b line] Signed-off-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Olliver Schinagl 提交于
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash storage. https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/ It is a assembly variant of the regular Lime2 but featuring eMMC for storage. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Emmanuel Vadot 提交于
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one. This makes the original node (mmc2_pins_a) scrapped out of the dtb and result in a unusable eMMC if U-Boot didn't configured the pins to the correct functions. Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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- 10 8月, 2017 14 次提交
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由 Marek Vasut 提交于
Allow sending restart conditions upon direction change as this is required by some chips. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: NHeiko Schocher <hs@denxx.de>
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由 Adam Ford 提交于
This converts the following to Kconfig: CONFIG_SYS_I2C_OMAP24XX Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Stefan Chulski 提交于
Set BM poll size once during priv probe and do not overwrite it during port probe procedure. Pool is common for all CP ports. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
TX drain in transmit procedure could cause issues due to race between drain procedure and transmition of descriptor between AGGR TXQ and physical TXQ. TXQ will be cleared before moving to Linux by stop procedure. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
MVPP22 driver support 64 Bit arch and require BM pool high address configuration. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
Remove IRQ configuration from U-Boot PP driver. U-Boot don't use interrupts and configuration of IRQ in U-Boot caused crashes in Linux shared interrupt mode. Also interrupt use is redundant in RX routine since a single RX queue is used. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
MBUS driver were replaced by AXI in PPv22 and relevant only for PPv21. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
U-boot use single physical tx queue with size 16 descriptors. So aggregated tx queue size should be equal to physical tx queue and cpu descriptor chunk(number of descriptors delivered from physical tx queue to aggregated tx queue by one chunk) shouldn't be larger than physical tx queue. Fix: Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as physical TXQ. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
Issue: BM counters were overrun by probe that called per Network interface and caused release of wrong number of buffers during remove procedure. Fix: Use probe_done and num_ports to call init and remove procedure once per communication controller. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
This patch enables padding of packets shorter than 64B in TX(set by default). Disabling of padding causes crashes on MACCIATO board. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1). Each communication controller has packet processor ports and MDIO. On MACHIATOBin board ports from CP1 are connected to mdio on CP0. Issue: Wrong base address is assigned to MDIO interface during probe. Fix: Get MDIO address from PHY handler parent base address. This should be refined in the future when MDIO driver is implemented. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
This patch add GPIO configuration support in mvpp2x driver. Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should be set in device tree. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 09 8月, 2017 6 次提交
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由 Adam Ford 提交于
The driver is for all boards 24XX and up, so let's eliminate the extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX. Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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Add missing probe function to the device driver to active a device. Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Tom Rini 提交于
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NTom Rini <trini@konsulko.com>
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- 08 8月, 2017 11 次提交
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由 Stefan Roese 提交于
This defconfig uses the PCIe x4 binary blobs from the congatec BIOS. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
- Disable debug UART - Enable more partition support Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
- Enable ACPI resume support - Disable debug UART - Enable Spansion and Winbond SPI flash support - Move VGA BIOS binary address to enable bigger U-Boot images Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This patch adds the common header include file theadorable-x86-common.h for the theadorable-x86 targets to define all common options and the default environment. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This patch adds the infrastructure to define different config headers with different configurations and default environment for the baseboards that can now be selected via Kconfig. The new configuration for the theadorable-x86-conga-qa3-e3845 is also added. Also the new defconfig file for this new target is added. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This patch adds the infrastructure to define different config headers with different configurations and default environment for the baseboards that can now be selected via Kconfig. The new configuration for the theadorable-x86-dfi-bt700 is also added. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
When CONFIG_EFI_PARTITION is not set, the following build error is seen in arch/x86/lib/acpi_s3.c: error: expected declaration specifiers or '...' before '*' token static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void*)WAKEUP_BASE; This is actually caused by missing asmlinkage declaration, but with CONFIG_EFI_PARTITION on, the declaration comes from part.h which is included from common.h. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Marek Vasut 提交于
This is defined twice in the same file, with the same value, likely because of some patch merge issue. Pick the uglier one and nuke it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
The I2C reading in the PEX vs SATA detection code often fails on the first try. Try three times, as the code for EEPROM reading does. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Bin Meng 提交于
Neither new design uses ISA bus, nor does any U-Boot codes use these codes. Remove them. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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